© 2010 Altera Corporation—Public Introducing 28-nm Stratix V FPGAs and HardCopy V ASICs: Built for Bandwidth 2010 Technology Roadshow

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Agenda The need for bandwidth The challenge Introducing 28-nm Stratix V FPGAs and HardCopy V ASICs Key innovations and benefits Summary 2

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Expanding Bandwidth Demands Mobile Internet Estimated 1.7B users by end of 2013 Fiber to the Home Estimated ~130M connections by end of 2013 Cloud Computing Hosted mobile applications estimated to reach 998M users by 2014 Mobile Backhaul Estimated 90,000 Gbps of capacity required by end of G Networks Expected to be 38% of worldwide market by end of 2013 LTE/WiMAX (4G ) ~5.6M users expected by end of

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Market Dynamics for High-End Systems Mobile Internet driving bandwidth at 50% annualized growth rate Fixed footprints Existing power ceilings 40G/100G system deployment with 200G/400G on the horizon CommunicationsBroadcastMilitaryComputer & Storage Worldwide proliferation of HD/1080p Move to digital cinema and 4K2K Fixed power budget Heightened intelligence and defense needs More sensors, higher precision driven to decision points faster Power and uptime critical Demand for Higher Bandwidth in Same Footprint at Same or Lower Power and Cost Higher bandwidth, performance and lower latency New interface standards with PCI Express Gen3 and QPI 4

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Increasing Bandwidth with Strict Power and Cost Budgets How to Increase Bandwidth, Without Increasing Cost or Power? Bandwidth Price/Power Time 5

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. TSMC’s High-Performance 28-nm Process 28-nm process advantages  2X the capacity  35% higher performance than alternative process options  Analog performance advantages enable faster and more power efficient transceivers  Enables 30% lower total power Altera’s patented process innovations address yield, performance, and power  Redundancy  Programmable Power Technology  Customized extra-low leakage devices 17-year relationship, with joint development First to 40 nm, First to 28 nm 6

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Innovations to Address the Challenge 28-nm high- performance process Embedded HardCopy Blocks Partial reconfiguration 12.5-Gbps transceivers 28-Gbps transceivers Highest Integration Ultimate Flexibility Highest Bandwidth Stratix V FPGAs and HardCopy V ASICs: A New Class of Devices, Ready for the Challenge HardCopy Block Enhanced Fabric with Partial Reconfiguration HardCopy Block 7

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Stratix V FPGAs – Built for Bandwidth Highest Bandwidth Hard IP and Flexibility IP Solutions and Ecosystem Highest bandwidth  66 transceivers capable of 12.5 Gbps and 7 x MHz DDR3 interfaces  Devices with 28-Gbps transceivers Unprecedented level of integration  Embedded HardCopy Blocks supporting PCI Express Gen3 and 40G/100G Ethernet  High-performance, high-precision DSP  Enhanced logic fabric with 1,100K LEs, 53 Mb RAM, and 3,680 18x18 multipliers Ultimate flexibility  Fine-grain and easy-to-use partial reconfiguration  Configuration via PCI Express 50% higher system performance and 30% lower power 8

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. HardCopy V ASICs – Risk-Free Path to ASIC Risk-free path to lower cost and up to 50% lower power with HardCopy V ASIC Up to 2X core performance improvement One design, one IP set, one tool delivers both FPGA and ASIC implementations Low NRE, with fast and predictable turnaround times Guaranteed first-time right Highest Bandwidth at Lowest Cost and Power No-Risk Path to Volume Production 9

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Stratix V Device Family Variants Stratix V GT FPGA  Optimized for applications requiring ultra-high bandwidth and performance with 12.5-Gbps and 28-Gbps transceivers Stratix V GX FPGA  For high-performance, high-bandwidth applications with transceivers up to 12.5 Gbps Stratix V GS FPGA  Optimized for ultra-high performance DSP, high-bandwidth applications with transceivers up to 12.5 Gbps Stratix V E FPGA  For highest density, high-performance applications 10

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Stratix V High-Bandwidth Transceivers Up to 66 identical, continuous-range, low-power, backplane-capable transceivers running at 150 Mbps to 12.5 Gbps Devices with 28-Gbps transceivers Sub-picoseconds jitter for best eye opening and system BER performance Dynamic reconfiguration of transceiver settings On-die instrumentation – EyeQ eye viewer per transceiver channel and 28-Gbps transceivers 11

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Stratix V FPGA On-Die Instrumentation View receiver signal margin with Altera’s EyeQ eye viewer Complete vertical/horizontal reconstruction of eye opening Engage in live debug while fine-tuning for ideal equalization Minimize Board Bring-Up/Debug Time with Dynamic Reconfiguration and EyeQ Tx Rx Lossy Medium Pre- Emphasis EQCDR EyeQ 12

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Extending Transceiver Leadership 2X the transceiver bandwidth at the same power 50% lower power per transceiver channel 200 mW per 28- Gbps transceiver or ~7mW/Gb Stratix V FPGAs Gbps Gbps8.5Gbps10.3Gbps11.3Gbps12.5Gbps Power (mW) Per Channel (PMA) Stratix V Transceivers: Highest Bandwidth and Power Efficiency 28Gbps Transceiver PMA Power Per Channel mW Per Gigabit (Gb) - 50% from 40 nm 13

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Highest memory bandwidth with up to 7 x72 DDR3 DIMMs with multi-rank support  Half the latency with the new UniPHY  Hard I/O FIFOs and read/write paths  High system reliability through duty cycle correction, calibration algorithms, and VT compensated deskew delays  Sharing of PLLs and DLLs across multiple interfaces Guaranteed timing closure and focus on user productivity and ease of use Delivering Highest Memory and I/O Performance and Bandwidth Stratix V Memory and I/O Performance Interface Performan ce DDR3800 MHz DDR2400 MHz QDR II333 MHz QDR II+550 MHz RLDRAM II533 MHz LVDS1.6 Gbps 14

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. The New Embedded HardCopy Block Used to harden standard or logic-intensive functions Reduces system cost and faster time to market Provides 2X performance enhancement 3-6 months turn-around time for new variants to address targeted applications 14M ASIC Gates/700K LEs with up to 65% Lower Power than Soft Implementation 15

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Partial Reconfiguration in Stratix V FPGAs Ultimate flexibility enabled by partial and dynamic reconfiguration No system downtime with dynamic updates Faster reconfiguration Reduces cost and power through integration Built on proven methodology using LogicLock™ and incremental compile A1 C1 D1E1 F1 B1 A2 C2 D1E1F1 B1 A2 C2 FPGA Core Partial Reconfiguration for the Core Transceivers Dynamic Reconfiguration for Transceivers #1 in Productivity and Performance 16

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Configuration Via PCI Express (CvPCIe) Initialize or update FPGA fabric via PCI Express (PCIe) Three steps for using CvPCIe  Program the PCIe hard IP (HIP) via serial SPI flash device  Program autonomous HIP before FPGA  CvPCIe completes programming of FPGA Always meet PCIe link bring-up time < 100ms Lower cost by using cheaper configuration file memory Faster configuration and enhanced system flexibility 4 pins Configure PCIe HIP PCIe Link Gen1/2/3 x1, x2, x4, x8 Load FPGA Image via PCIe Link Serial SPI Flash PCIe Hard IP Endpoint Host PC 17

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Altera Leads the Way Again in Fabric Innovation Higher Logic Efficiency and System Performance Enhanced adaptive logic module (ALM) with 4 registers 5.5X more routing connections than competing devices Enhanced embedded memory structure for more memory bits and ports with M20K Faster MLAB blocks and support for wide shallow FIFOs High-resolution clock synthesis with up to 32 fractional PLLs More clock sources and networks with the ability to power down unused logic 18

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. The Need for Variable Precision in DSP Addresses the key challenge of supporting multiple precision requirements of various systems 9x9 12x12 18x18 18x36 27x27 36x36 54x54 DSP SYSTEM PRECISION VIDEO WIRELESS, MEDICAL MILITARY, TEST, HP COMPUTING 19

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. First Variable-Precision DSP Block DSP Precision Modes Three independent 9x9One complex 27x27 (four cascaded blocks) Two independent 18x18 (32-bit resolution)One complex 18x25 (three cascaded blocks) One independent 27x27Sum of two 18x18 One independent 18x36Sum of four 18x18 (two cascaded blocks) One independent 36x36 (two cascaded blocks)Sum of two 18x36 (two cascaded blocks) One independent 54x54 (four cascaded blocks)Sum of two 27x27 (two cascaded blocks) Additional features for more efficient implementation of DSP algorithms /26-bit pre-adder 2. Internal coefficient storage bit accumulator bit cascade bus

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Highest System Performance on 28 nm TSMC’s high-performance process 50% increase in memory interface performance 1.6-Tbps serial switching capability Enhanced core fabric 1,840 GMACS of signal- processing performance Embedded HardCopy Blocks for 2X performance vs. soft logic 800-MHz DDR3 DIMM 12.5-/28-Gbps Serial Transceivers Embedded Hardcopy Blocks 600-MHz Memory Blocks Enhanced ALM and Routing 50% Increase in System Performance Up to 3,680 Variable- Precision DSP Blocks 21

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Stratix V Technologies to Control Power Power Reduction Method Lower Static Power Lower Dynamic Power 28-nm process innovations Programmable Power Technology Customized extra-low leakage devices Lower core voltage (0.85 V) Extensive hardening of IP, Embedded HardCopy Blocks Hard power-down of functional blocks More granular clock gating Partial reconfiguration DDR3 and dynamic on-chip termination Quartus II software PowerPlay power optimization 30% Lower Total Power 22

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. A Complete Solution Design Software Intellectual Property SOPC Builder Advanced DSP Builder Embedded Soft-Core Processors 23

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Highest bandwidth with and 28-Gbps transceivers Highest level of system integration through extensive hard IP integration and the new Embedded HardCopy Blocks 50% higher system performance at 30% lower total power Ultimate flexibility with easy-to-use partial reconfiguration Lowest risk path to HardCopy V ASICs Productivity advantage with Quartus II software system solutions, tools, and IP for vertical markets Stratix V FPGAs and HardCopy V ASICs Built for Bandwidth 24

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Learn More Download the white paper  Introducing Innovations at 28 nm to Move Beyond Moore’s Law Download the Stratix V Device Handbook 25

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