GlueX Collaboration Oct '06 C. Cuevas 1 Topics: Projects and Progress 250Msps Flash ADC Energy Sum Module The Bigger Picture DAQ/Electronics Work Plans Overall Electronic ‘System’ Concerns & Issues GlueX Collaboration Meeting Jefferson Lab October 2006 ELECTRONICS R. Chris Cuevas Jefferson Lab Physics Division Group Leader -- Fast Electronics

GlueX Collaboration Oct '06 C. Cuevas 2 Flash ADC Development At the IU Electronics meeting in April 2006 the detailed requirements were reported as a “work in progress”: We have completed all of the design requirements for the prototype and created several documents: Msps Flash ADC Module Specifications 2.Flash ADC FPGA requirements (V4LX25) a)Data Processing and Trigger Window Latency b)Energy Sum (8 channels per FPGA) c)Hit Bit Output d)Trigger Processing – Buffering up to 4 consecutive triggers without data loss 3.Flash ADC Interface and communication with FPGAs 4.Flash ADC Data format for readout 5.Flash ADC Internal Data format – On board FPGA to FPGA 6.Flash ADC Hit Bit Processing, ADC summing & MGT transmission (V4FX20) 7.Flash ADC JTAG and FPGA Eprom configuration and control

GlueX Collaboration Oct '06 C. Cuevas 3 Flash ADC Status - Prototype Block Diagram This diagram is not intended for extreme details, and has not been updated recently. The diagram shows the important decisions for FPGA selection and other hardware features. Schematic The Schematic is a tremendous amount of effort and is 47 pages!! Clearly the work of several engineers and designers. Printed Circuit Board The latest layout is shown on a slide that follows. Power regulators and other power components will be finalized soon and full time work for routing will begin soon. Components XC4VFX20 parts ordered and received. These parts have all 8 MGT units operational at 3.125Gbps. 10 bit Maxim ADC parts ordered and received. XCLX25 parts have been received. All other parts are stock items and we will purchase enough for two prototype units.

GlueX Collaboration Oct '06 C. Cuevas 4

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7 Flash ADC Development Milestones This module is a very challenging design and the progress is remarkable, given that the design team members are committed to other projects also.  October Design Complete [ Schematic reviewed]  November-December 2006 – Final layout/Routing/Review/Order  January-March 2007 – INTENSE TESTING! This will include software development work for Coda ‘Drivers’ and Test Station.  Summer 2007 – Production modules,, “How many would you like to order?”

GlueX Collaboration Oct '06 C. Cuevas 8 Energy SUM Module Development The prototype module is assembled and initial testing is complete. The design engineer left the lab in August, so firmware development has not progressed. The energy sum prototype module will allow us to continue the research necessary to gain expertise with the new VXS, { VME with serial extensions} technology. We have purchased the necessary test instruments for measuring the MultiGigabit Transceivers, and have evaluated several VXS crates from different manufacturers.

GlueX Collaboration Oct '06 C. Cuevas 9 Quick VXS Review Why VXS? VXS provides an infrastructure for multi-GBps switched serial technologies to compete and grow on top of VME Expected to extend the life of VME for decades –Part of the VME Renaissance Pro’s –Very high bandwidth –Low latency –Increased scalability (as compared to a bus architecture) –Less contention (as compared to a bus architecture) –Experiment with switched serial under the safety of the parallel bus –Migrate from parallel bus to serial switched at one’s own pace –Provides a platform for high availability systems – hot swap

GlueX Collaboration Oct '06 C. Cuevas 10 Quick VXS Review VXS Backplane VXS “Switch” Card (Jlab Energy Sum) VXS “Payload” (Jlab fADC )

GlueX Collaboration Oct '06 C. Cuevas 11 More VXS Fun 21 Slot VXS crate from Wiener Plein & Baus Note Switch Slots are Located in the 1 st and Last slots. VME64x Slot is included that Does not have the P0 Or MGT connector

GlueX Collaboration Oct '06 C. Cuevas 12 More VXS Fun 21 Slot VXS crate from Wiener Plein & Baus The absolute latest In high speed serial Analysis with digital Oscilloscope technology Was delivered in Sept! Tektronix 8Ghz BW Digital Serial Analyzer

GlueX Collaboration Oct '06 C. Cuevas 13 VXS Test Plan CH1 CH16 FPGAFPGA FPGAFPGA FPGAFPGA CH8 CH9 VME P0VXS Jefferson Lab FLASH ADC PENTEK 6822 ADC CH1 CH2 VME P0VXS FPGAFPGA FPGAFPGA Jefferson Lab VXS “Switch Slot” Crate SUM “GateFlow” High Speed Serial VITA 41 Backplane FPGAFPGA 16 Channel Board SUM Data DAC Crate SUM To Main Trigger

GlueX Collaboration Oct '06 C. Cuevas 14 VXS Test Plan

GlueX Collaboration Oct '06 C. Cuevas 15 VXS Testing FIFO “0000” “0000” ADD FIFO 16 FIFO TEST CODE FOR PENTEK BOARD Produced by: Doug Curry 16 AURORA 64 CHIP SCOPE 12 U1 U2 U1_U2_SUM Loopback Module in Switch Slot ADC1(U1) ADC2(U2)

GlueX Collaboration Oct '06 C. Cuevas 16 VXS Testing Figure 3: VXS Loopback Waveform results (Xilinx ChipScope Pro) Test Conditions: Input ADC1: BLUE  Negative exponential pulse Input ADC2: RED  Negative exponential pulse; Inverted and attenuated (14db) 1Mhz Input Frequency for both inputs Output ADC1_Aurora: GREEN  Data transmitted round trip for ADC1 Output ADC1_ADC2_SUM: MAGENTA  ADC1 + ADC2 result transmitted round trip Conclusion: The backplane functions correctly for the given payload assignment. Four high speed serial ‘lanes’ are used at 2Gbps for an aggregate transfer rate of 8Gbps. The Aurora protocol appears to have a latency of approximately 400ns roundtrip, but the proper summing function occurs without error and is extremely stable. Further testing with the Pentek module is planned to achieve the maximum serial transfer rating of the Xilinx VirtexII Pro FPGA. The Jlab switch slot design will allow the testing of two Jlab flash ADC prototype modules and the Pentek module.

GlueX Collaboration Oct '06 C. Cuevas 17 The Bigger Picture DAQ/Electronics Work Plans Hall D Electronics System Integration & Engineering Concerns & Issues

GlueX Collaboration Oct '06 C. Cuevas 18 GlueX- Doc DAQ/Electronics Work Plans *Note: Two Xilinx development Modules received for CNU to Prototype and test crate summing Information to Master Trigger

GlueX Collaboration Oct '06 C. Cuevas 19 Hall D Electronics System Integration & Engineering Engineering effort for the Electrical/Electronics Systems of Hall D is significant. This ‘system’ includes (but is not limited to): 1.Civil Construction – AC power distribution & grounding 2.Control/Monitor systems for power supplies and instrument racks 3.Beamline instrumentation 4.Detector Electronics Instrumentation a.Tagger b.Collimator c.Start Counter d.Central Drift Chamber – Preamplifiers e.BCAL – SiPMT f.FDC – Preamplifiers g.TOF h.Cerenkov i.FCAL 5.HV system(s) 6.Readout electronics CABLING! (Including Low Voltage)

GlueX Collaboration Oct '06 C. Cuevas 20 Hall D Electronics System Integration & Engineering

GlueX Collaboration Oct '06 C. Cuevas 21 Concerns & Issues Electronics Coordinator – Paul Smith has accepted a new position at IU Will the collaboration provide a new coordinator? The work required for the new Readout/Daq/Trigger Electronics Will need additional manpower to meet proposed schedules. Collaborating groups have committed to building Detector systems and other important electronic projects such as the Preamplifiers, Tagger instrumentation, and 64-Channel ADC for the wire chambers. This goes back to the 1 st bullet,, Technician position has been posted, and another Engineer position has been requested,,, These positions are crucial to meet the Jlab Electronics Plan goals.

GlueX Collaboration Oct '06 C. Cuevas 22 Roll the credits,,, Design efforts are remarkable and I thought I would be appropriate to acknowledge: Fernando Barbosa Electronics Group Hai Dong Electronics Group Jeff WilsonElectronics Group Mark TaylorElectronics Group William GunningElectronics Group Ed JastrzembskiDaq Group David AbbottDaq Group David DoughtyCNU