Overview of the read-out electronics for the TPCs at T2K ND280m P. Baron, D. Calvet, X. De La Broïse, E. Delagnes, F. Druillole, J-L Fallou, J-M. Reymond, E. Virique, E. Zonca DSM/DAPNIA/SEDI, CEA Saclay Gif-sur-Yvette Cedex, France

Paris 12 September Plan Context TPC Read-out Architecture Summary

Paris 12 September TPC Configuration Features 3 TPCs stations; each with 2 planes of 2 x 6 detector modules Each detector module: Micromegas, cm square Module segmentation: 1728 pads of 9.7 mm x 6.9 mm Total number of pads: space points in z-axis, (2.5 mm spacing) 3 TPC stations 1 m 2.5 m x y z Detector module

Paris 12 September Outline of Requirements Non Functional and Environmental Compact, low power, modest magnetic field (0.2 T), no radiation Underground experiment (Japan), fire and seismic safety rules Functional and Performance Noise, dynamic range, resolution, linearity SNR=100 (i.e. 700 e - rms for 12 fC MIP), 10 MIP on 12 bits, 1-5% Event rate: ~0.3 Hz spill + cosmic. For DAQ: 20 Hz mean and max. 512 space points, various gas: µs drift (1.25 m drift distance) Support for GEM and Micromegas charge amplification technology Demands on front-end electronics and data acquisition Highly segmented detector (124 k channels) Extreme burstiness of initial data (several Tbaud/s peak) Large event size (90 MB) but modest event rate (few Hz) → Strategy: re-use ALTRO based electronics for detector R&D; while designing new read-out electronics

Paris 12 September Complete Logical Read-Out Flow Architecture principles Front-end ASIC with analog memory (Switch Capacitor Array) ADC + digital buffer mounted close to the detector Multiple optical fibers send data to off-detector concentrators Interface to common DAQ via standard network Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer Data concentration ~ channels 1728 Front end ASICs On-detector electronics 72 Optical fibers 1-6 Tbaud*/s peak *1 baud = 10 bit ~2 ms retention max. 34 Gbaud/s peak 400 Gbit/s peak ~1-10 Gbit/s averaged Shared DAQ system ~0.1-1 Gbit/s Standard LAN connection(s) 432 Front end cards 6 Concentrator Cards 72 Mezzanines

Paris 12 September Detector Module Read-out 72 modules in total 72-channel ASIC Quad-channel ADC digital Front-end Mezzanine card (FEM) Optical Transceiver FPGA 80-pin connector 288-channel analog Front-End Card (FEC) 1728-pad detector plane Slow-control network Fiber to DCC Power bar Low- voltage power

Paris 12 September TPC Plane Readout Off-detectorInside the Magnet 1 of 6 TPC planes shown – 3 TPC stations 6 x 2 detector modules per TPC plane – 72 modules in total 1 duplex optical readout fiber per detector module 1 external data concentrator per TPC plane – 6 concentrators in total Data Concentrator Card Detector Module 12 optical fibers Front- End Card TPC plane Front-End Mezzanine card Optical link x 6

Paris 12 September TPC Event Building, DAQ Interface Principles Event Building for TPC data over backplane bus with a PC or each concentrator send data directly to the DAQ via a LAN connection Interface to common DAQ system via standard Gigabit Ethernet LAN TPCs (like other detectors) compliant to the experiment wide physical interface specifications, protocols and software framework TCP/IP Commercial Linux PC 6 concentrators VME/PCI backplane bus Gigabit Ethernet Network Common DAQ Run Control Detector B Detector A Detector TPCs Global Clock Trigger

Paris 12 September Front-end ASIC Synopsis Serial Interface Trigger CK In Test 512 cells SCA FILTER Tpeak;Gain CSA 1 channel X64 BUFFER SLOW CONTROL TESTSCA MANAGER StopCK ADC Asic T2K GAIN Number of channels72Sampling frequency1MHz to 50MHz Number of Time bins511Shaping Time100ns to 2µs MIP12fC to 60fC Read out frequency 20 to 25MHz MIP/noise100Signal PolarityNegative (TPC) or positive Dynamic range10 MIPS on 12bitsCalibration Selection 1/72 I.N.L1% [0-3 MIPS];5% [3-10 MIPS]Test1 capacitor / channel GainAdjustable (4 values)

Paris 12 September Front-end ASIC: AFTER AFTER : Asic For Tpc Electronic Read-out Technology: AMS CMOS 0.35  m Area: 7546  m x 7139  m Submission: 24 April 2006 Delivered: end of July Package: LQFP 160 pins; Plastic dimensions: 30mm x 30mm thickness: 1.4mm pitch: 0.65mm Number of transistors: 400,000 SCA: 76x511 Cells

Paris 12 September Analog Front-end Card Features –6 Analog Front-end cards per detector module; i.e. 432 cards in total –Throughput: 0.96 Gbps per card, 414 Gbps total –Plugs at the back of detector plane; inside the magnet – water cooling –Conceptual design in progress – first prototype expected Q2-Q ASIC 4 channel ADC Passive Components Connectors to detector plane 288 channel FE card Digital output ~25 cm ~14 cm

Paris 12 September ASIC Test Card Features –Essentially FEC pre-prototype; 4 ASICs (1 socketed) –Board under assembly; expected in the next few days ZIF Socket Interface connector to FEM

Paris 12 September Connector Evaluation: Detector R&D The GEM and Micromegas detector R&D on HARP used the proposed connector on the protection card → Proposed connector is now validated Protection Card Prototype Micromegas Detector plane

Paris 12 September Digital Front-end Mezzanine Card Architecture –Commercial FPGA, memory and optical transceiver –Target: Xilinx Virtex-2 Pro / Virtex 4 with RocketIO transceiver –Design in progress – supports 4-6 FE cards –First prototype: end 2006; i.e. 6 months after number of FE card frozen Analog FE Card Clock Trigger Control Data 1.2 Gbit/s peak Analog FE Card Analog FE Card Analog FE Card FPGA Logic Memory ~6 Mbit ~5 Gbit/s ~12 Mbit/s ~5 Gbit/s Clock Trigger Control Optical Link Average rate < 50 Mbit/s Digital Front end Mezzanine Card

Paris 12 September Reduced FEM card Architecture –Daughter card for a commercial Memec FPGA kit; can drive one FEC → Setup used for ASIC test, and prototype boards validation

Paris 12 September Off-Detector Concentrator Card Principles Standard form factor (6U or 9U); VME or Compact PCI backplane bus Clock, trigger and control signals fanout, slow control interface FPGA logic VME or PCI Optical transceivers Main data 1-2 Gbit/s Slow control data Slow control commands Global clock Trigger Global clock Trigger Slow control Main data

Paris 12 September Integration, Resources On-detector Electronics Power supplies and power distribution, forced cooling; 3 kW Common/shared services Trigger generation Global clock source and inter-detector synchronization DAQ hardware interface and software Slow control, configuration, monitoring Racks, type of crate, common hardware/software platforms Cooling water and heat exchanger Resources for TPC electronics ~30 FTE (Saclay, Lpnhe, Barcelona); investment: ~480 k€ Planning 1 TPC detector module equipped with prototypes in mid-2007 Mass production of electronic cards and tests in 2008 Installation and commissioning for operation in April 2009