Content Project Goals. Term A Goals. Quick Overview of Term A Goals. Term B Goals. Gantt Chart. Requests.

Project Goal Using the open source single core OpenRISC 1200 CPU to implement a multicore system. The OpenRISC 1200 is a synthesizable CPU core maintained by developers at OpenCores. The OR1200 design is an open source (under LGPL GNU) implementation of the OpenRISC 1000 RISC architecture.

Term A Primary Goal: building an OpenRISC based system on FPGA. Configuring the CPU. Building a SoC. Simulation and Synthesis Implementation Debugging Benchmarking for future reference.

OR1200 Block Diagram

OR1200 Based SoC

Term A Secondary Goal: choosing a multicore architecture.

Background Needed Logic Design. Computer architecture. OpenRISC architecture. Multicore architectures. Wishbone bus. Verilog. FPGA tools. Linux toolchain (uClib,binutils, GCC, GDB).

Project Layers

Challenges The work is done on multiple levels, from a hardware RTL design to a C software. We aren’t working just with OR1200, but an entire SoC. Numerous units and different architectures go into the design. Hardware and software together. The lack of proper documentation for several components of the system.

Term B Primary Goal: building a SoC based on a multicore implementation of the OpenRISC. Choosing multicore architecture. Choosing the number of cores (could it be dynamic ?). Designing, implementing and debugging the system. Benchmarking.

Where Are We Now We finished most of the reading, Still need to read about: Wishbone bus. Verilog (partial). The real work starts now We should have synthesis of the system in the next 4-6 weeks.

Gantt chart

Requests VirtualBox: open source software under GNU GPL. allows the guest OS to run on virtual environment within the host OS. VirtualBox Extension pack: allows the guest OS access to the USB. FPGA: Xilinx XUP5. Extra HD space: 15GB in total. Virtualbox base image = 5GB Virtualbox image with development tools = 8GB Source code of the core = 3GB 15% extra space

Thank you.