Novel Wire Density Driven Full-Chip Routing for CMP Variation Control Huang-Yu Chen †, Szu-Jui Chou †, Sheng-Lung Wang ‡, and Yao-Wen Chang † † National Taiwan University, Taiwan ‡ Synopsys, Inc, Taiwan

2 Outline  CMP Introduction  Previous Work  Wire-Density Driven Two-Pass Top-Down Routing  Experimental Results  Conclusion

3 Outline  CMP Introduction  Previous Work  Wire-Density Driven Two-Pass Top-Down Routing  Experimental Results  Conclusion

4 Cu Damascene Process  The Cu metallization (Damascene) contains two main steps: electroplating (ECP) and chemical-mechanical polishing (CMP)  ECP: deposits Cu on the trenches  CMP: removes Cu that overfills the trenches  Great interconnect performance and systematic yield loss are observed after CMP ECPCMPOpen trenches

5 CMP Process  CMP contains both chemical and mechanical parts  Chemically: abrasive slurry dissolves the wafer layer  Mechanically: a dynamic polishing head presses pad and wafer Schematic diagram of CMP polisher Slurry Polishing pad Polishing head Wafer

6 layout pattern density  Post-CMP topography strongly depends on underlying layout pattern density  Uneven layout density leads to metal dishing and dielectric erosion after CMP Layout-Dependent Thickness Variations Oxide polishing pad slurry dielectric metal Post-CMPPre-CMP metal dielectric dishing erosion

7 Layout Pattern Density Control wire dummy density rulesdummy features  Foundries have set density rules and filled dummy features to improve CMP quality  Disadvantages of dummy fills: 1. Changes coupling capacitance of interconnects 2. Leads to explosion of mask data, putting heavy burdens to following time-consuming RETs  Routing  Routing considering uniform wire density helps control the layout pattern density  Avoid aggressive post-routing dummy fills

8 Outline  CMP Introduction  Previous Work  Wire-Density Driven Two-Pass Top-Down Routing  Experimental Results  Conclusion

9 Minimum Pin Density Global Routing minimum pin density  Cho et al. [ICCAD’06] selected paths with minimum pin density to reduce maximum wire density in global tiles  Paths with lower pin density tend to have lower wire density and can get much benefit from optimization p1p1 p2p2 2 possible 1-bend S  T pathsPath a with lower density S T S T Select path p 1 with lower pin density p1p1

10 Wire Density-Driven Cost Function  Li et al. [TCAD’07] set the cost function of a global tile t to guide a wire density-driven global router: : capacity of t : demand of t : parameter of target density (=4 for 25% target density) 1

11 inside  Both approaches only consider the wire density inside a routing tile inter-tile  It may incur larger inter-tile density difference  results in irregular post-CMP thickness variations Limitations Post-CMP Thickness Density = 0.4Density = 0.1 Need to minimize the density difference among global tiles

12 Outline  CMP Introduction  Previous Work  Wire-Density Driven Two-Pass Top-Down Routing  Experimental Results  Conclusion

13 Multilevel Routing  A modern chip may contain billions of transistors and millions of nets  Multilevel routing  Multilevel routing has been proposed to handle large- scale designs Already-routed net To-be-routed net coarseninguncoarsening ‧ global routing ‧ detailed routing ‧ failed nets rerouting ‧ refinement Λ-shaped multilevel routing

14 high low Two-Pass Top-Down Routing Framework G0G0 G1G1 G2G2 Planarization- aware top-down global routing 1 st Pass Stage Top-down detailed routing and refinement 2 nd Pass Stage Voronoi-diagram based density critical area analysis (CAA) Prerouting Stage uncoarsening G0G0 G1G1 G2G2 Density-driven layer assignment and Delaunay-triangulation track assignment Intermediate Stage To-be-routed net Already-routed net

15 Top-Down Routing Approach 1.Planarity is a long-range effect 2.Longer nets shall be planned first  greater impacts/determination for density  usually hard to predict paths 3.Bottom-up routing easily falls into local optima  over density may occur among subregions ? ? ? Bottom-up routing Over density among subregions G0G0 G1G1 G2G2 ?

16 Density Analysis Prerouting G0G0 G1G1 G2G2 Planarization- aware top-down global routing 1 st Pass Stage Top-down detailed routing and refinement 2 nd Pass Stage uncoarsening G0G0 G1G1 G2G2 Density-driven layer assignment and Delaunay-triangulation track assignment Intermediate Stage To-be-routed net Already-routed net high low Voronoi-diagram based density critical area analysis (CAA) Prerouting Stage

17 Density Critical Area Analysis (CAA)  Performs density analysis to guide following routing pin distributionVoronoi diagrams  Given a routing instance, we predict density hot spots based on the pin distribution by Voronoi diagrams

18 Voronoi Diagram Voronoi diagram Voronoi cells  The Voronoi diagram of a point set decomposes space into non-overlapping Voronoi cells  If a point q lies in the Voronoi cell of p, then q would be close to p than other points q p

19 Observation of Voronoi Diagrams  Non-uniform distribution leads to large area variation among Voronoi cells Non-uniform distributionUniform distribution

20 Density Hot Spots Identification  If the Voronoi cell of a pin has more adjacent cells, density hot spots may occur around it pin density  Define pin density of a pin p as # of adjacent Voronoi cells completely sitting inside a range from p p pin density = 3

21 Global Tile Predicted Density  Map pin density to global tiles to guide global routing  The predicted density of a global tile t: Pin densityPredicted density of global tile = max{ pin density | pin locates within t }

22 high low Voronoi-diagram based density critical area analysis (CAA) Prerouting Stage 1 st Pass Top-Down Global Routing Top-down detailed routing and refinement 2 nd Pass Stage uncoarsening G0G0 G1G1 G2G2 Density-driven layer assignment and Delaunay-triangulation track assignment Intermediate Stage To-be-routed net Already-routed net G0G0 G1G1 G2G2 Planarization- aware top-down global routing 1 st Pass Stage

23  Objectives: 1. Encourage each global tile to satisfy density upper- and lower-bound rules 2. Minimize the density difference among global tiles Planarization-Aware Global Routing Post-CMP Thickness Density = 0.5Density = Wire density map Density =

24 : predicted density of t (prerouting density CAA) Planarization-Aware Cost Function  Planarization-aware cost of global tile t with density d t : : positive penalty (> 0) : average density of tiles around t : user-define parameter : negative reward (< 0)

25 G0G0 G1G1 G2G2 Planarization- aware top-down global routing 1 st Pass Stage high low Voronoi-diagram based density critical area analysis (CAA) Prerouting Stage Intermediate Layer/Track Assignment Top-down detailed routing and refinement 2 nd Pass Stage uncoarsening G0G0 G1G1 G2G2 To-be-routed net Already-routed net Density-driven layer assignment and Delaunay-triangulation track assignment Intermediate Stage

26 Density-Driven Layer Assignment  Goal: to evenly distribute segments to layers panel densitylocal density  Minimizes the panel density while balancing the local density of each layer  local density: # of segments and obstacles in a column  panel density: maximum local density among all columns Chip layout (aerial view)

27 s6s6 o1o s1s1 s2s2 s3s3 s4s4 s5s5 o2o s1s1 s2s2 s4s4 s5s5 s6s6 o2o2 o1o1 s3s Density-Driven Layer Partitioning horizontal constraint graph  Builds horizontal constraint graph HCG(V,E)  Node: segment and obstacle  Cost of an edge (v i, v j ): maximum local density of overlapping columns between v i and v j max-cut, k-coloring  Partitions layer groups by max-cut, k-coloring algorithms

s1s1 s2s2 s4s4 s5s5 s6s6 o2o2 o1o1 s3s Minimum-Impact Repair Procedure  For the fixed-layer obstacle which is not assigned to the correct layer  Exchanges its layer with the layer of a connected segment whose edge cost is the maximum s1s1 s2s2 s4s4 s5s5 s6s6 o2o2 o1o1 s3s3 Exchange layer of obstacle O 1 with that of S 6

29 Density-Driven Layer Assignment Result Layer 1 Layer 3

30 Density-Driven Track Assignment  Goal: to keep segments spatially separated in a panel Delaunay Triangulation  Uses good properties of Delaunay Triangulation (DT)  Represents each segment by three points, two end points and one center point, and analyzes the DT  Non-uniform segment distribution  large area difference among triangles in DT Non-uniform distributionUniform distribution

31 Artificial Segment artificial segment  Model the density distribution of each neighboring panel into an artificial segment lying on the boundary  Length: the average occupied length per track  Center: the center of gravity of all segments and obstacles susu sbsb

32 Delaunay-Triangulation Track Assignment flexibility  Define flexibility of a segment s i,  t i : number of assignable tracks for s i  l i : length of s i  Insert segments in the non-decreasing order of flexibility  Each segment is assigned to the track that minimizes the area difference among all triangles of DT s2s o1o1 sbsb susu ξ (s 3 ) = 3+1/8 = ξ (s 2 ) = 4+1/1 = 5 ξ (s 1 ) = 4+1/2 = 4.5 s3s3 s1s1

33 A Density-Driven Track Assignment Example o1o1 s3s3 ξ (s 2 ) = 4 ξ (s 1 ) = 4.5 s2s o1o1 s3s3 s2s o1o1 s3s3 s1s1 sbsb susu Segment Artificial segment Layer 1 obstacle

34 Outline  CMP Introduction  Previous Work  Wire-Density Driven Two-Pass Top-Down Routing  Experimental Results  Conclusion

35 Experimental Setting  C++ language with LEDA library on a 1.2 GHz Sun Blade-2000 with 8GB memory  Compared our two-pass, top-down routing system (TTR) with MROR [Li et al., TCAD’07] Λ-shaped multilevel router considering balanced density  Compared the density-CAA guided global routing of TTR with CMP-aware minimum pin-density global routing [Cho et al., ICCAD’06] Minimum pin-density global routing + TTR detailed routing

36 Routing Benchmarks  Academic: eleven MCNC benchmarks  Industrial: five Faraday benchmarks MCNC benchmarks Faraday benchmarks

37 Comparison Metric  Comparison is based on the same metric used in the work of MROR [TCAD’07]  #Net max : maximum # of nets crossing a tile  #Net avg_h : average # of nets horizontally crossing a tile  #Net avg_v : average # of nets vertically crossing a tile  σ h : standard deviation of # of nets horizontally crossing a tile  σ v : standard deviation of # of nets vertically crossing a tile  Reflects the wire density distribution for a routing result

38 Experimental Results (MCNC)  All three routers achieved 100% routability  TTR reduced  #Net max by 43% than TCAD’07 and 11% than ICCAD’06  #Net avg_v by 34% than TCAD’07 and 5% than ICCAD’06  #Net avg_h by 36% than TCAD’07 and 11% than ICCAD’06

39 Vertical Wire Crossing of S MROR [TCAD’07] GR [ICCAD’06] +TTR framework TTR (Ours)

40 Experimental Results (Faraday)  MROR [TCAD’07] cannot run designs where pins are distributed between layers 1 and 3  TTR reduced  #Net max by 25% than ICCAD’06  #Net avg_v by 2% than ICCAD’06  #Net avg_h by 2% than ICCAD’06

41 Horizontal Wire Crossing of RISC1 GR [ICCAD’06] +TTR detailed routing TTR (Ours)

42 Outline  CMP Introduction  Previous Work  Wire-Density Driven Two-Pass Top-Down Routing  Experimental Results  Conclusion

43 Conclusion  Proposed a new full-chip density-driven routing system for CMP variation control 1. Voronoi-diagram based density CAA prerouting 2. Planarization-aware top-down global routing 3. Density-driven layer assignment + Delaunay-triangulation based track assignment 4. Top-down detailed routing  Reduced 43% and 11% maximum wire crossing on density tiles and achieved more balanced wire distribution than state-of-the-art previous works

44 Q & A Thanks for your attention!