Fall 2010, Nov 16ELEC / Guest Lecture1 ELEC / Fall 2010 VLSI Design Low Power VLSI Design Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Fall 2010, Nov 16ELEC / Guest Lecture2 Power Consumption of VLSI Chips Why is it a concern?

Fall 2010, Nov 16ELEC / Guest Lecture3 ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor....” Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP.

Fall 2010, Nov 16ELEC / Guest Lecture4 VLSI Chip Power Density Pentium® P Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

Fall 2010, Nov 16ELEC / Guest Lecture5 Low-Power Design Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. Low-power design methods: Low-power design methods: Algorithms and architectures Algorithms and architectures High-level and software techniques High-level and software techniques Gate and circuit-level methods Gate and circuit-level methods Test power Test power

Fall 2010, Nov 16ELEC / Guest Lecture6 Specific Topics in Low-Power Power dissipation in CMOS circuits Power dissipation in CMOS circuits Transistor-level methods Transistor-level methods Low-power CMOS technologies Low-power CMOS technologies Energy recovery methods Energy recovery methods Ultra low power logic (subthreshold VDD) Ultra low power logic (subthreshold VDD) Circuit and gate level methods Circuit and gate level methods Logic synthesis Logic synthesis Dynamic power reduction techniques Dynamic power reduction techniques Leakage power reduction Leakage power reduction System level methods System level methods Microprocessors Microprocessors Arithmetic circuits Arithmetic circuits Low power memory technology Low power memory technology Test Power Test Power Power estimation Power estimation

Fall 2010, Nov 16ELEC / Guest Lecture7 CMOS Logic (Inverter) F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid- State Circuits Conference Digest, vol. IV, February 1963, pp No current flows from power supply! Where is power consumed? VDD GND

Fall 2010, Nov 16ELEC / Guest Lecture8 Components of Power Dynamic, when output changes Dynamic, when output changes Signal transitions (major component) Signal transitions (major component) Logic activity Logic activity Glitches Glitches Short-circuit (small) Short-circuit (small) Static, when signal is in steady state Static, when signal is in steady state Leakage (used to be small) Leakage (used to be small) P total =P dyn + P stat =P tran + P sc + P stat

Fall 2010, Nov 16ELEC / Guest Lecture9 Power of a Transition: P tran V Ground C R = R on Large resistance v i (t) v(t) i(t) C =Total load capacitance for gate; includes transistor capacitances of driving gate + routing capacitance + transistor capacitances of driven gates; obtained by layout analysis.

Fall 2010, Nov 16ELEC / Guest Lecture10 Charging of a Capacitor V C R i(t) i(t) v(t) Charge on capacitor, q(t)=C v(t) Current, i(t)=dq(t)/dt=C dv(t)/dt t = 0

Fall 2010, Nov 16ELEC / Guest Lecture11 i(t)=C dv(t)/dt=[V – v(t)] /R dv(t) dt ∫ ───── = ∫ ──── V – v(t) RC – t ln [V – v(t)]=──+ A RC Initial condition, t = 0, v(t) = 0 → A = ln V – t v(t) =V [1 – exp(───)] RC

Fall 2010, Nov 16ELEC / Guest Lecture12 – t v(t)=V [1 – exp( ── )] RC dv(t) V – t i(t)=C ───=── exp( ── ) dt R RC

Fall 2010, Nov 16ELEC / Guest Lecture13 Total Energy Per Charging Transition from Power Supply ∞∞ V 2 – t E trans =∫ V i(t) dt=∫ ── exp( ── ) dt 00 R RC =CV 2

Fall 2010, Nov 16ELEC / Guest Lecture14 Energy Dissipated Per Transition in Resistance ∞ V 2 ∞ – 2t R ∫ i 2 (t) dt=R ── ∫ exp( ── ) dt 0 R 2 0 RC 1 = ─ CV 2 2

Fall 2010, Nov 16ELEC / Guest Lecture15 Energy Stored in Charged Capacitor ∞∞ – t V – t ∫ v(t) i(t) dt = ∫ V [1 – exp( ── )] ─ exp( ── ) dt 00 RC R RC 1 = ─ CV 2 2

Fall 2010, Nov 16ELEC / Guest Lecture16 Transition Power Gate output rising transition Gate output rising transition Energy dissipated in pMOS transistor = CV 2 /2 Energy dissipated in pMOS transistor = CV 2 /2 Energy stored in capacitor = CV 2 /2 Energy stored in capacitor = CV 2 /2 Gate output falling transition Gate output falling transition Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated per transition = CV 2 /2 Energy dissipated per transition = CV 2 /2 Power dissipation: Power dissipation: P trans =E trans α f ck =α f ck CV 2 /2 α=activity factor f ck = clock frequency

Fall 2010, Nov 16ELEC / Guest Lecture17 Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage P total =P dyn + P stat =P tran + P sc + P stat

Fall 2010, Nov 16ELEC / Guest Lecture18 Short Circuit Power of a Transition: P sc V DD Ground CLCL v i (t) v o (t) i sc (t)

Fall 2010, Nov 16ELEC / Guest Lecture19 Short-Circuit Power Increases with rise and fall times of input. Increases with rise and fall times of input. Decreases for larger output load capacitance; large capacitor takes most of the current. Decreases for larger output load capacitance; large capacitor takes most of the current. Small, about 5-10% of dynamic power dissipated in charging and discharging of the output capacitance. Small, about 5-10% of dynamic power dissipated in charging and discharging of the output capacitance. Becomes zero when V DD ≤ V thn + V thp Becomes zero when V DD ≤ V thn + V thp

Fall 2010, Nov 16ELEC / Guest Lecture20 Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage

Fall 2010, Nov 16ELEC / Guest Lecture21 Static (Leakage) Power Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. For a gate it is a small fraction of the total power; it can be significant for very large circuits. For a gate it is a small fraction of the total power; it can be significant for very large circuits. Static power increases as feature size is scaled down; controlling leakage is an important aspect of transistor design and semiconductor process technology. Static power increases as feature size is scaled down; controlling leakage is an important aspect of transistor design and semiconductor process technology.

Fall 2010, Nov 16ELEC / Guest Lecture22 CMOS Gate Power V Ground C R = R on Large resistance v i (t) v(t) i(t) time v i (t) i(t) i sc (t) Leakage current

Fall 2010, Nov 16ELEC / Guest Lecture23 Some Examples

Energy Saving by Voltage Reduction Battery size VDD = 0.9V, 500MHzVDD = 0.3V, 5MHz Efficiency % Battery lifetime Efficiency % Battery lifetime AHr x10 3 seconds x10 11 cycles x10 3 seconds x10 11 cycles Fall 2010, Nov 16ELEC / Guest Lecture24 seven-times  70 million gate circuit, 45nm CMOS bulk PTM.  Lithium-ion battery.  Ref.: M. Kulkarni and V. D. Agrawal, “A Tutorial on Battery Simulation – Matching Power Source to Electronic System,” Proc. VLSI Design and Test Symp., July 2010.

Fall 2010, Nov 16ELEC / Guest Lecture25 State Encoding for a Counter Two-bit binary counter: Two-bit binary counter: State sequence, 00 → 01 → 10 → 11 → 00 State sequence, 00 → 01 → 10 → 11 → 00 Six bit transitions in four clock cycles Six bit transitions in four clock cycles 6/4 = 1.5 transitions per clock 6/4 = 1.5 transitions per clock Two-bit Gray-code counter Two-bit Gray-code counter State sequence, 00 → 01 → 11 → 10 → 00 State sequence, 00 → 01 → 11 → 10 → 00 Four bit transitions in four clock cycles Four bit transitions in four clock cycles 4/4 = 1.0 transition per clock 4/4 = 1.0 transition per clock Gray-code counter is more power efficient. Gray-code counter is more power efficient. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Kluwer Academic Publishers (now Springer), 1998.

Fall 2010, Nov 16ELEC / Guest Lecture26 Binary Counter: Original Encoding Present state Next state abAB ABAB a b CK CLR

Fall 2010, Nov 16ELEC / Guest Lecture27 Binary Counter: Gray Encoding Present state Next state abAB ABAB a b CK CLR

Fall 2010, Nov 16ELEC / Guest Lecture28 Three-Bit Counters BinaryGray-code State No. of toggles State Av. Transitions/clock = 1.75 Av. Transitions/clock = 1

Fall 2010, Nov 16ELEC / Guest Lecture29 N-Bit Counter: Toggles in Counting Cycle Binary counter: T(binary) = 2(2 N – 1) Binary counter: T(binary) = 2(2 N – 1) Gray-code counter: T(gray) = 2 N Gray-code counter: T(gray) = 2 N T(gray)/T(binary) = 2 N-1 /(2 N – 1) → 0.5 T(gray)/T(binary) = 2 N-1 /(2 N – 1) → 0.5 BitsT(binary)T(gray)T(gray)/T(binary) ∞

Fall 2010, Nov 16ELEC / Guest Lecture30 FSM State Encoding Expected number of state-bit transitions: 1( ) + 2(0.1) = 1.0 Transition probability based on PI statistics State encoding can be selected using a power-based cost function. 2( ) + 1( ) = 1.6

Fall 2010, Nov 16ELEC / Guest Lecture31 FSM: Clock-Gating Moore machine: Outputs depend only on the state variables. Moore machine: Outputs depend only on the state variables. If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self-loop is to be executed. If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self-loop is to be executed. Sj Si Sk Xi/Zk Xk/Zk Xj/Zk Clock can be stopped when (Xk, Sk) combination occurs.

Fall 2010, Nov 16ELEC / Guest Lecture32 Clock-Gating in Moore FSM Combinational logic Latch Clock activation logic Flip-flops PI CK PO L. Benini and G. De Micheli, Dynamic Power Management, Boston: Springer, 1998.

Fall 2010, Nov 16ELEC / Guest Lecture33 Bus Encoding for Reduced Power Example: Four bit bus Example: Four bit bus 0000 → 1110 has three transitions → 1110 has three transitions. If bits of second pattern are inverted, then 0000 → 0001 will have only one transition. If bits of second pattern are inverted, then 0000 → 0001 will have only one transition. Bit-inversion encoding for N-bit bus: Bit-inversion encoding for N-bit bus: Number of bit transitions 0 N/2N N N/2 0 Number of bit transitions after inversion encoding

Fall 2010, Nov 16ELEC / Guest Lecture34 Bus-Inversion Encoding Logic Polarity decision logic Sent data Received data Bus register Polarity bit M. Stan and W. Burleson, “Bus-Invert Coding for Low Power I/O,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp , March 1995.

Fall 2010, Nov 16ELEC / Guest Lecture35 Clock-Gating in Low-Power Flip-Flop D Q D CK

S5378 with Gated-Clock FF 2958 gates, 179 flip-flops 2958 gates, 179 flip-flops TSMC025 CMOS TSMC025 CMOS 1,000 random vectors, clock period 50ns 1,000 random vectors, clock period 50ns Simulation by Powersim* Simulation by Powersim* Fall 2010, Nov 16ELEC / Guest Lecture36 Flip- flops used Power (microwatts) Combinational logic ClockFlip-flopsTotal Transitions Short- circuit Static (leakage) Normal ,081.5 Gated J. D. Alexander, “Simulation Based Power Estimation for Digital CMOS Technologies,” Master’s Thesis, Auburn University, Dec *

Fall 2010, Nov 16ELEC / Guest Lecture37 Books on Low-Power Design (1) L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Boston: Springer, M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Boston: Springer, R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley- Interscience, J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley- Interscience, J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997.

Fall 2010, Nov 16ELEC / Guest Lecture38 Books on Low-Power Design (2) N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley- Interscience, K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley- Interscience, E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston:Springer, W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston:Springer, S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: springer, G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: springer, G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, 2004.

Fall 2010, Nov 16ELEC / Guest Lecture39 Books Useful in Low-Power Design A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw-Hill, R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw-Hill, S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts: Addison-Wesley, N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts: Addison-Wesley, 2005.

Fall 2010, Nov 16ELEC / Guest Lecture40 Problem: Bus Encoding A 1-hot encoding is to be used for reducing the capacitive power consumption of an n-bit data bus. All n bits are assumed to be independent and random. Derive a formula for the ratio of power consumptions on the encoded and the un-coded buses. Show that n ≥ 4 is essential for the 1-hot encoding to be beneficial. Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995, pp [Hint: You should be able to solve this problem without the help of the reference.]

Fall 2010, Nov 16ELEC / Guest Lecture41 Solution: Bus Encoding Un-coded bus: Two consecutive bits on a wire can be 00, 01, 10 and 11, each with a probability Considering only the 01 transition, which draws energy from the supply, the probability of a data pattern consuming CV 2 energy on a wire is ¼. Therefore, the average per pattern energy for all n wires of the bus is CV 2 n/4. Encoded bus: Encoded bus contains 2 n wires. The 1-hot encoding ensures that whenever there is a change in the data pattern, exactly one wire will have a 01 transition, charging its capacitance and consuming CV 2 energy. There can be 2 n possible data patterns and exactly one of these will match the previous pattern and consume no energy. Thus, the per pattern energy consumption of the bus is 0 with probability 2 –n, and CV 2 with probability 1 – 2 –n. The average per pattern energy for the 1-hot encoded bus is CV 2 (1 – 2 –n ).

Fall 2010, Nov 16ELEC / Guest Lecture42 Solution: Bus Encoding (Cont.) Power ratio =Encoded bus power / un-coded bus power =4(1 – 2 –n )/n → 4/n for large n For the encoding to be beneficial, the above power ratio should be less than 1. That is, 4(1 – 2 –n )/n ≤ 1, or 1 – 2 –n ≤ n/4, or n/4 ≥ 1 (approximately) → n ≥ 4. The following table shows 1-hot encoded bus power ratio as a function of bus width: n 4(1 – 2 – n )/n n = 1/ / /16