PACS IBDR 27/28 February 2002 PACS DEC/MEC1 Detectors & Mechanisms Controllers (DEC/MEC) J.-M. Gillis Centre Spatial de Liège (B)

PACS IBDR 27/28 February 2002 PACS DEC/MEC2 Content models design status interface status test results expected performances, budgets procurement, manufacturing & AIV plan schedule milestones product assurance problems areas & critical items

PACS IBDR 27/28 February 2002 PACS DEC/MEC3 Models AVM EM QM FM

PACS IBDR 27/28 February 2002 PACS DEC/MEC4 Design Status - Hardware DEC –CRE I/F updated following modified CRE spec & cryoharness –SPICE model DEC/CRE I/F, simulated power ON/OFF, noise –boards design nearing completion ( EM level ) –1355 FPGA operational ( non redundant version ) link reliability test : > disconnect/reconnect –DEC FPGA operational, integrated in DEC SIM for AVM –next tasks : testing of DEC SIM in AVM, 100% validation of DEC/MEC I/F manufacturing of EM boards ( 2 “base” + 4 “dec” ) interface validation ( 13 CRE cluster = 1 supply 4K ) FPGA final versions ( with sync and redundancy logic ) integration with OBS, 100% testing of HK & TC

PACS IBDR 27/28 February 2002 PACS DEC/MEC5 DEC - FPGA status IIDR ( 3 CRE proto ) => IBDR ( 13 CRE FPGA )

PACS IBDR 27/28 February 2002 PACS DEC/MEC6 Design Status - Hardware MEC : MIM ( Mechanisms Interface Module ) –HK HK board prototype running, to be updated for T° sensors, in use for developing low level software –Grating grating drive validated on separate test system, prototype board for EM in design, to be updated for actual DC/DC –Chopper chopper drive prototype HW in manufacturing –Filter wheel filter wheel drive prototype HW in manufacturing –Calibration sources calibration sources drive prototype HW in manufacturing

PACS IBDR 27/28 February 2002 PACS DEC/MEC7 Design Status - Hardware MEC : DSP –MOSAIC board integrated in AVM, operational –EM prototype hardware running –EM board in fabrication at CRISA –electrical and mechanical interfaces frozen –timing FPGA ( CSL ) validated ( MOSAIC version ) - to be updated for CRISA board + possible merging with MIM DC/DC –architecture designed (1 filter + 1 MEC + 2 relays + 2 DEC) –EM specification done –compliant offer received –manufacturer selected

PACS IBDR 27/28 February 2002 PACS DEC/MEC8 Design Status - On Board Software “High level” layer –DPU interface tested with simulators ( ongoing ) –SPU interface tested with simulators ( ongoing ) –BOLC interface not tested –DEC interface tested with software hardware simulator –interface with low level specified –1355 code to be adapted for CRISA board “Low level” layer –Interrupt handler triggered by timing FPGA, jitter spec OK –readout of HK board validated –motor control, synchronization, black body interface : in development –code for AVM : representative timing & CPU load

PACS IBDR 27/28 February 2002 PACS DEC/MEC9 Development Status - On Board Software “High level” size ( in text lines ) –Total lines : 9582 –Non-comment lines : 4965 –C files lines : 3010 –real code lines : 2000 “Low level” size ( in assembler instructions ) –typical application ( grating cryoprototype ) : 240 lines –housekeeping data acquisition ( on Mosaic ) : 20 –ISR overhead ( context switch etc... ) : 6 –total asm code : 100 instr X 5 cycles X 8192/sec = 23% load not included : libraries ( Virtuoso services ) current executable size : PM = 20 Kw, DM = 16 Kw

PACS IBDR 27/28 February 2002 PACS DEC/MEC10 Development Status - On Board Software detailed design / prototype coding status –Sequencer : 100% –DPU communication : 100% –SPU communication : 100% –housekeeping : 100% –DEC communication : 40% ready to start integration and test with DEC SIM hardware –BOLC communication : 40% –Mechanisms control : 30% prototype developed outside OBS structure High/low layers interface specification under review coding status –simulator and on board software use same source code –code configuration control implemented

PACS IBDR 27/28 February 2002 PACS DEC/MEC11 Design Status - Mechanical Layout SVM accomodation : one box ( similar to BOLC ) dimensions : (L x W x H) ~ 585 x 320 x 320 connector allocation from cryoharness specification preliminary front panel design preliminary box drawing board list and updated mass estimate available iteration needed with prime

PACS IBDR 27/28 February 2002 PACS DEC/MEC12 Interface Status - Overview

PACS IBDR 27/28 February 2002 PACS DEC/MEC13 Interface Status - ICDs

PACS IBDR 27/28 February 2002 PACS DEC/MEC14 Results achieved / current tests CRE interface –measurements done with real 4K with DEC proto ( IMEC report available ) –manufacturing cryo test bench ( 13 4K + DEC EM ) BOLC interface –Spacewire communication design from CEA validated by CSL –Interface test with BOLC simulator planned 03/2002 (TBC) DPU & SPU interfaces –Ongoing : integration testing with software simulators Mechanisms –prototype boards ready, low level software in development –tests planned : Grating : done, Chopper TBD, Filter wheel 03/2002, Calibration source 05/2002, Temp sensors TBD

PACS IBDR 27/28 February 2002 PACS DEC/MEC15 Performance & Budgets Data handling : CPU workload 50 % TBC w/AVM –estimation down, measured some real code, within budget Measurement quality : within noise spec in lab –first results with 1 CRE, coming tests with full supply group Mass & dimensions : iteration required w/prime Power : will probably not decrease –current estimates : 20 to 67 W depending on mode

PACS IBDR 27/28 February 2002 PACS DEC/MEC16 Procurement & Manufacturing

PACS IBDR 27/28 February 2002 PACS DEC/MEC17 Schedule Milestones

PACS IBDR 27/28 February 2002 PACS DEC/MEC18 Problem Areas / Critical Items Mass / volume / SVM accomodation –current estimates above initial IID-B figures - iteration req’d Grating encoder readout –CPPA problems ( rad. tolerance ) [ > keep & shield ] Cryoharness –not confirmed to spec, awaiting evaluation samples mechanism simulators availability