1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 3 CPUs.

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Presentation transcript:

1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 3 CPUs

2 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.1 Structure of a typical I/O device.

3 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.2 The interrupt mechanism.

4 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.3 Prioritized device interrupts.

5 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.4 Using polling to share an interrupt over several devices.

6 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.5 Interrupt vectors.

7 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.6 The cache in the memory system.

8 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.7 A two-level cache system.

9 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.8 A direct-mapped cache.

10 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.9 A set-associative cache.

11 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.10 A virtually addressed memory system.

12 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.11 Segments and pages.

13 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.12 Address translation for a segment.

14 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.13 Address translation for a page.

15 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.14 Alternative schemes for organizing page tables.

16 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.15 ARM two-stage address translation.

17 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.16 Pipelined execution of ARM instructions.

18 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.17 Pipelined execution of multicycle ARM instructions.

19 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.18 Pipelined execution of a branch in ARM.

20 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.19 A power state machine for a processor.

21 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.20 UML collaboration diagram for the data compressor.

22 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.21 Definition of the data-compressor class.

23 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.22 Additional class definitions for the data compressor.

24 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.23 Relationships between classes in the data compressor.

25 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.24 State diagram for encode behavior.

26 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.25 State diagram for insert behavior.

27 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.26 A test of the encoder.

28 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.1

29 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.2

30 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.3

31 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.4

32 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.5

33 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.6

34 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.7

35 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.8

36 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.9

37 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.10

38 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.11

39 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 3.12