1 Moore’s Law – the Z dimension Sergey Savastiouk, Ph.D. April 12, 2001

2 Introduction: The next dimension is the Z dimension Step 1: Vertical miniaturization – thinning –Thinner is better –Thinning and handling problems and solutions Step 2: Vertical integration – stacking –Thru-Silicon vias –3D stacking for system-in-a-chip (SIP) Conclusion: 3D Wafer Level Packaging Presentation Overview Presentation Overview

Moore’s Law – the X-Y dimensions. The number of components on a surface of a chip would double every 18 – 24 months.

4 ? Si Moore’s Law - the Z dimension The number of components in 3D space would double every 18 – 24 months.

5 Packaging trends

6 Package and Chip Thickness

7 Wafer and Chip Thickness

8 Step 1: Vertical miniaturization – thinning Thinner is better Why to thin? Step 1: Vertical miniaturization – thinning Thinner is better Why to thin?

9 Thinner is better u WHY to thin ? u Better packaging density u More flexible u More reliable u Better thermal resistance u Better yields 50  m wafer.

10 Reduction of thickness by half provides 50% reduction in height and 30% in footprint of packaging Si H1 H2 Si Thinning for smaller space: Why to thin?

11 <100 micron thickness for improved reliability, requires damage-free silicon Hitachi Thinning for flexibility: Why to thin ?

12 Numerical results for reliability: Why to thin ? Thick chip: u = 700  m, b = 1000  m Thin chip: u = 50  m, b = 200  m

13 Improved Power Dissipation: Why to thin?

14 Step 1: Vertical miniaturization – thinning Thinning and handling problems and solutions How to thin? How to handle thinned wafers? Step 1: Vertical miniaturization – thinning Thinning and handling problems and solutions How to thin? How to handle thinned wafers?

15 Thinning alternatives Grinding (leaves damage) Polishing (leaves some damage) Wet etching (removes damage, but wet) Dry etching (removes damage) Silicon Damage

16 Si WAFER No induced electrical damage No vacuum pumps – excellent process control Etch rate suitable for mass production Atmospheric Downstream Plasma: How to thin?

17 Edge damage yield problems: How to handle? Damaged edges cause wafers to break

18 NoTouch™ wafer holding: How to thin? Atmospheric Downstream Plasma Holding Gas NoTouch Holder Wafer Back Side Maintains planarity of flexible wafers No contact with bumps

19 Silicon Damage Silicon No damage Damage-free wafer surface: How to thin ?

20 Damage free edges: How to thin?

21 After wet spin etching After grinding or polishingOld technologies After ADP etching New ADP technology Thinning alternatives: How to thin?

22 Die strength etching vs. grind & CMP: How to thin?

23 Wafer warp improvement

24 Damage Free Dicing (in development) Step 2. Controlled depth dicing Step 3. Apply top side tape Step 1. Grind Individual dice Step 4. Etch the backside to singulate

25 DBG vs. Damage Free Dicing DBG vs. Damage Free Dicing Sawed die showing chipping 40 micron thin ADP etched dice, rounded and smoothed Chip Shifts and Cracks No Chip Shifts and Cracks

26 Damage Free Dicing SEM pictures of the edges Die top

27 Step 2: Vertical integration – stacking How to thin and to bump on a backside in one step? How to stack? Step 2: Vertical integration – stacking How to thin and to bump on a backside in one step? How to stack?

28 Integration: SOC vs. SOB,SIP ? SIP SOB SOC

29 ADP Via Etch (continued)

30 ADP thinning of via ADP thinning of via (continued)

31 Thru-Silicon via

32 Back Side of a wafer with contact pad Thru-Silicon via results Silicon Metal SiO 2

33 Thru-Silicon via results Back side of a wafer with contact pads

34 Tru-CSP™ for front side up : project

35 Tru-CSP™ for opto-electronics: project

36 Tru-CSP™ with passive interposer : project

37 Tru-CSP™ face-to-face : project

38 Tru- 3D Stacking Tru- 3D Stacking : project

, $8m raised, ADP prototyping 1998, Ultra-thin handling prototyping 1999, $10m raised, Product development 2000, System sales and Thru-Silicon dev-t 2001, $18m raised, – Thru-Silicon dev-t hiring process engineers: Conclusion: History of Company

40 Thinning by ADP and NoTouch handling: – enables low cost damage free thinning – enables low cost damage free dicing Thinning by ADP with Thru-Silicon vias: – enables the new generation of low cost 3D stacking methods of chips and wafers for System-In-a-Package – brings front-end technologies to back-end applications Conclusion: Overall Summary