Basics of State Machine Design

Finite-State Machines (FSMs) Want sequential circuit with particular behavior over time Example: Laser timer Push button: x=1 for 3 clock cycles How? Let’s try three flip-flops b=1 gets stored in first D flip-flop Then 2nd flip-flop on next cycle, then 3rd flip-flop on next OR the three flip-flop outputs, so x should be 1 for three cycles Controller x b clk laser patient

Need a Better Way to Design Sequential Circuits Trial and error is not a good design method Will we be able to “guess” a circuit that works for other desired behavior? How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10 cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input? And, a circuit built by guessing may have undesired behavior Laser timer: What if press button again while x=1? x then stays one another 3 cycles. Is that what we want? Combinational circuit design process had two important things: A formal way to describe desired circuit behavior Boolean equation, or truth table A well-defined process to convert that behavior to a circuit We need those things for sequential circuit design

Describing the Behavior of a Sequential Circuit: FSM Outputs: x On O ff x=0 x=1 clk ^ Finite-State Machine (FSM) A way to describe desired behavior of sequential circuit Akin to Boolean equations for combinational behavior List states, and transitions among states Example: Make x change toggle (0 to 1, or 1 to 0) every clock cycle Two states: “Off” (x=0), and “On” (x=1) Transition from Off to On, or On to Off, on rising clock edge Arrow with no starting state points to initial state (when circuit first starts)

FSM Example: 0,1,1,1,repeat Want 0, 1, 1, 1, 0, 1, 1, 1, ... Outputs: x On1 O ff On2 On3 clk ^ x=1 x=0 Want 0, 1, 1, 1, 0, 1, 1, 1, ... Each value for one clock cycle Can describe as FSM Four states Transition on rising clock edge to next state O ff On1 On2 On3 clk x State Outputs:

Extend FSM to Three-Cycle Laser Timer On2 On1 On3 O ff clk ^ x=1 x=0 b ’*clk b*clk Inputs: b; Outputs: x Four states Wait in “Off” state while b is 0 (b’) When b is 1 (and rising clock edge), transition to On1 Sets x=1 On next two clock edges, transition to On2, then On3, which also set x=1 So x=1 for three cycles after button pressed Description is explicit about what happens in “repeat input” case!

FSM Simplification: Rising Clock Edges Implicit ff x=1 x=0 b’ clk ^ *clk b Inputs: b; Outputs: x Showing rising clock on every transition: cluttered Make implicit -- assume every edge has rising clock, even if not shown What if we wanted a transition without a rising edge We don’t consider such asynchronous FSMs -- less common, and advanced topic Only consider synchronous FSMs -- rising edge on every transition On2 On1 On3 Off x=1 x=0 b ’ Inputs: b; Outputs: x Note: Transition with no associated condition thus transistions to next state on next clock cycle

FSM Definition FSM consists of Set of states Inputs: b; Outputs: x On2 On1 On3 Off x=1 x=0 b ’ FSM consists of Set of states Ex: {Off, On1, On2, On3} Set of inputs, set of outputs Ex: Inputs: {b}, Outputs: {x} Initial state Ex: “Off” Set of transitions Describes next states Ex: Has 5 transitions Set of actions Sets outputs while in states Ex: x=0, x=1, x=1, and x=1 We often draw FSM graphically, known as state diagram Can also use table (state table), or textual languages

FSM Example: Secure Car Key Many new car keys include tiny computer chip When car starts, car’s computer (under engine hood) requests identifier from key Key transmits identifier 4-bits, one bit at a time If not, computer shuts off car FSM Wait until computer requests ID (a=1) Transmit ID (in this case, 1101) K1 K2 K3 K4 r=1 r=0 Wait Inputs: a; Outputs: r a ’

FSM Example: Secure Car Key (cont.) Nice feature of FSM Can evaluate output behavior for different input sequence Timing diagrams show states and output values for different input waveforms K1 K2 K3 K4 r=1 r=0 W ait I nputs: a ; O utputs: r ’ Q: Determine states and r value for given input waveform: W ait K1 K2 K3 K4 clk I nputs O utputs S t a e r clk I nputs a W ait K1 K2 K3 K4 Output State r K1

FSM Example: Code Detector Unlock door (u=1) only when buttons pressed in sequence: start, then red, blue, green, red Input from each button: s, r, g, b Also, output a indicates that some colored button is being pressed FSM Wait for start (s=1) in “Wait” Once started (“Start”) If see red, go to “Red1” Then, if see blue, go to “Blue” Then, if see green, go to “Green” Then, if see red, go to “Red2” In that state, open the door (u=1) Wrong button at any step, return to “Wait”, without opening door s Start u r Door Red Code g lock Green detector b Blue a Wait Start Red1 R ed2 Green Blue s ’ a r b g ab ag ar u=0 u=1 Inputs: s,r,g,b,a; Outputs: u Q: Can you trick this FSM to open the door, without knowing the code? A: Yes, hold all buttons simultaneously

Improve FSM for Code Detector Inputs: s,r,g,b,a; Outputs: u Wait s’ ar’ ab’ ag’ ar’ u=0 s Start a ’ u=0 ar ab ag ar Red1 Blue Green Red2 a ’ a ’ a ’ u=0 u=0 u=0 u=1 Note: small problem still remains; we’ll discuss later New transition conditions detect if wrong button pressed, returns to “Wait” FSM provides formal, concrete means to accurately define desired behavior

Common Pitfalls Regarding Transition Properties Only one condition should be true For all transitions leaving a state Else, which one? One condition must be true Else, where go?

Verifying Correct Transition Properties Can verify using Boolean algebra Only one condition true: AND of each condition pair (for transitions leaving a state) should equal 0  proves pair can never simultaneously be true One condition true: OR of all conditions of transitions leaving a state) should equal 1  proves at least one condition must be true Example a * a’b = (a * a’) * b = 0 * b = 0 OK! Answer: a + a’b = a*(1+b) + a’b = a + ab + a’b = a + (a+a’)b = a + b Fails! Might not be 1 (i.e., a=0, b=0) Q: For shown transitions, prove whether: * Only one condition true (AND of each pair is always 0) * One condition true (OR of all transitions is always 1)

Evidence that Pitfall is Common Recall code detector FSM We “fixed” a problem with the transition conditions Do the transitions obey the two required transition properties? Consider transitions of state Start, and the “only one true” property Wait s ’ u=0 s Start a ’ u=0 ar ab ag ar Red1 Blue Green Red2 a ’ a ’ a ’ u=0 u=0 u=0 u=1 ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g) = (a*a’)r = 0*r = (a’*a)*(r’+b+g) = 0*(r’+b+g) = (a*a)*r*(r’+b+g) = a*r*(r’+b+g) = 0 = 0 = arr’+arb+arg = 0 + arb+arg = arb + arg = ar(b+g) Fails! Means that two of Start’s transitions could be true Intuitively: press red and blue buttons at same time: conditions ar, and a(r’+b+g) will both be true. Which one should be taken? Q: How to solve? A: ar should be arb’g’ (likewise for ab, ag, ar) Note: As evidence the pitfall is common, the author of this example admitted the mistake was not intentional – A reviewer of his book caught it.

Design Process using FSMs Determine what needs to be remembered What will be stored in memory? Encode the inputs and outputs in binary (if necessary) Construct a state diagram of the behavior of the desired device Optionally – minimize the number of states needed Assign each state a binary number (code) Choose a flip-flop type to use Derive the flip-flop input maps Produce the combinational logic equations and draw the schematic from them

Example Design 1 Design a circuit that has input w and output z All changes are on the positive edge of the clock The output z = 1 only if w = 1 for both of the two preceding clock cycles Note: z does not depend on the current w Sample timing: cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 w: 1 z:

Steps 1 & 2 What needs to be remembered? Previous two input values If both are 1, then z = 1 at next positive clock edge Possible “states” are A: seen 10 or 00  output z = 0 B: seen 01  output z = 0, but we’re almost there! C: seen 11  output z = 1 Step 2 is trivial since the inputs and outputs are already in binary

Step 3 Corresponding state diagram C z 1 = ¤ B A w

Step 4 Assign binary numbers to states Many assignments are possible Since there are 3 states, we need 2 bits 2 bits  2 flip-flops Many assignments are possible One obvious one is to use: A: 00 (or 10 instead) B: 01 C: 11 This choice may not be “optimal” State assignment is a complex topic all to itself!

State Diagram / State Table 11 z 1 = ¤ 01 00 w next state current state w = 0 w = 1 Q2 Q1 Q2 Q1 z 0 0 0 1 1 1 1 x x x

General Form of Design A 2 flip-flop design now has the form w Combinational circuit Clock z w

Step 5 Choose a flip-flop type Regardless of type of flip-flop chosen The choice DOES impact the cost of the circuit The choice need not be the same for each flip-flop Regardless of type of flip-flop chosen Need to derive combinational logic for each flip-flop input in terms of w and current state Use K-maps for minimum SOP for each Need to derive combinational logic for z in terms of w and current state Use K-map for this also Suppose we choose D type …

D Flip-Flop Input Maps Q2Q1 w 00 01 11 10 x 1 D2 = w Q1 Q2Q1 w 00 01 next state Q2Q1 w 00 01 11 10 x 1 current state w = 0 w = 1 Q2 Q1 Q2 Q1 z 0 0 0 1 1 1 1 x x x D2 = w Q1 Q2Q1 w 00 01 11 10 1 x Q2Q1 w 00 01 11 10 x 1 z = Q2 D1 = w

D Flip-Flop Implementation

Variation: JK Flip-Flop Input Maps Suppose we use 2 JK flip-flops … This takes more work, but often results in very efficient implementations Q2Q1 w 00 01 11 10 x 1 J2 = w Q1 next state Q2Q1 w 00 01 11 10 x 1 current state w = 0 w = 1 Q2 Q1 Q2 Q1 z 0 0 0 1 1 1 1 x x x K2 = w'

JK Flip-Flop Input Maps for Q1 Q2Q1 w 00 01 11 10 x 1 next state current state w = 0 w = 1 Q2 Q1 Q2 Q1 z 0 0 0 1 1 1 1 x x x J1 = w Q2Q1 w 00 01 11 10 x 1 K1 = w'

JK Flip-Flop Implementation

Variation: T Flip-Flop Input Maps Suppose we use 2 T flip-flops instead … Note that the output z is unaffected by the choice of flip-flop and so does not change Q2Q1 w 00 01 11 10 1 x T2 = w Q2'Q1+w'Q2 next state Q2Q1 w 00 01 11 10 1 x current state w = 0 w = 1 Q2 Q1 Q2 Q1 z 0 0 0 1 1 1 1 x x x T1 = w'Q1+wQ1'

Excitation Tables It's very helpful to keep a list of the various flip-flop excitation tables nearby Either keep this close by, or make sure you can always reproduce it Q(t) Q(t+1) D T SR JK 0x 1 10 1x 01 x1 x0

A Different State Assignment 10 z 1 = ¤ 01 00 w Different state assignments can have quite an effect on the resulting implementation cost next state current state w = 0 w = 1 Q2 Q1 Q2 Q1 z 0 0 0 1 1 1 0 x x x

Resulting D Flip-Flop Input Maps Q2Q1 w 00 01 11 10 x 1 next state current state w = 0 w = 1 Q2 Q1 Q2 Q1 z 0 0 0 1 1 1 0 x x x D2 = w Q1 + w Q2 = w (Q1+Q2) Q2Q1 w 00 01 11 10 x 1 D1 = w Q2' Q1'

New D Flip-Flop Implementation Cost increases due to extra combinational logic

Moore FSM A finite state machine in which the outputs do not directly depend on the input variables is called a Moore machine Outputs are usually associated with the state, since they do not depend on the input values Also note that the choice of flip-flop does not change the output logic Only one K-map need be done regardless of the choice of flip- flop type

Mealy FSM If the output does depend on the input, then the machine is a Mealy machine This is more general than a Moore machine If required, then Mealy machine. If not required, then Moore machine. Combinational circuit Flip-flops Clock Q W Z

Mealy Design Example 1 Redesign the “sequence of two 1's” example so that the output z = 1 in the same cycle as the second 1 Compare the Moore and Mealy model outputs: Moore model Mealy model cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 w: 1 z: cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 w: 1 z:

Mealy FSM Mealy machines have outputs associated with the transitions Moore machines have outputs associated with the states – that's why the output does not depend on the input A w = z ¤ 1 B

State Table Only 2 states needed, so only 1 flip-flop required State A: 0 State B: 1 A w = z ¤ 1 B next state output current state w = 0 w = 1 Q z 1

Output Logic The outputs still do not depend on the choice of flip- flops, but they do depend on the inputs next state output current state w = 0 w = 1 Q z 1 Q w 1 Q w 1 D = w z = w Q

D Flip-Flop Implementation z = 1since w = 1 on both sides of posedge clock z = 0 since w = 0 even though no posedge clock has occurred – level sensitive output!

Converting Mealy to Moore Mealy machines often require fewer flip-flops and/or less combinational logic But output is level sensitive To modify a Mealy design to behave like a Moore design, just insert a D flip-flop to synchronize the output

Modified Mealy  Moore Design

Verilog for FSM

CAD Automation of Design As usual, CAD tools can automate much of the design process, but not all of it Deriving the state diagram is still an art and requires human effort Obviously, we could design everything and then just implement the design using schematic capture Or … we can use Verilog to represent the FSM and then allow the CAD tool to convert that FSM into an implementation Automates state assignment, flip-flop selection, logic minimization, and target device implementation

Repeat of Design Principles The design process is about determining the two combinational circuits below and linking them by flip- flops next state current state Combinational circuit Clock z w Y y Y y

Verilog for Moore Style FSMs C z 1 = ¤ B A w ResetN=0 state transition logic flip-flops required z = 1 if previous two consecutive w inputs were 1 – Moore machine style output logic

Coding Style The Verilog coding style is very important You need to code in such a way that the Verilog compiler can effectively use FSM techniques to create good designs Use of the parameter statement or `define is a must for detecting FSM specifications Also, note that testing whether your design is correct can be a challenge The two faces of CAD: synthesis and verification How much testing is enough testing? What does “testing” look like? Use input test vectors and check the outputs for correctness

An Alternate Moore Coding Style Same example, but only one always block Both approaches work well in CAD tools

Register Swap Controller B Rout2=1 Rin3=1 A C Rout1=1 Rin2=1 D Rout3=1 Rin1=1 Done=1 Enable=0 Enable=1 Enable=0,1

Bus Controller Bus controller receives requests for access to a shared bus Requests on separate lines: R0, R1, R2, R3 Controller grants request via a one-asserted output 4 separate grant lines G0, G1, G2, G3: one asserted Priority given to lowest numbered device device 0 > device 1 > device 2 > device 3 No interrupts allowed Device uses bus until it relinquishes it

Bus Controller FSM 5 states A: bus idle B: device 0 using the bus C: device 1 using the bus D: device 2 using the bus E: device 3 using the bus R[0:3] = 0000 0000 A / G[0:3] = 0000 A/0000 notation used

Complete FSM for Bus Controller A/0000 0000 B/1000 1xxx C/0100 x1xx D/0010 xx1x E/0001 xxx1 0xxx 01xx x0xx 001x xx0x 0001 xxx0

Verilog for Bus Controller

Alternate Verilog for Bus Controller

Idle Cycle in Design Note that when a device de-asserts its request line, a cycle is wasted in returning to the idle state (A) If another request were pending at that time, why can't the bus controller simply transfer control to that device? It can, but we need a more complex FSM for that Same number of states, just many more transitions

Permitting Preemption Once a device is granted access, it controls the bus until it relinquishes control Higher priority devices must wait Can we change the behavior so that high priority devices can preempt lower priority devices and take over control? Of course! Can we combine preemption with the removal of the idle cycle? Yes ….

Complete FSM for Bus Controller A/0000 0000 B/1000 1xxx C/0100 x1xx D/0010 xx1x E/0001 xxx1 0xxx 01xx x0xx 001x xx0x 0001 xxx0

Preemption Without the Idle Cycle A/0000 0000 B/1000 1xxx C/0100 01xx 001x E/0001 0001 D/0010

vending machine controller Deliver one pack of gum for 15 cents So it’s cheap gum. So what! Maybe it's just one stick. One slot for all coins Can detect nickels and dimes separately We’ll assume that you can’t insert BOTH a nickel and a dime in the same clock cycle No change given! vending machine controller nickel detected dime detected clock release gum

Verilog for Mealy Style FSMs w = z ¤ 1 B Mealy outputs are associated with the transitions