Introduction to Sequential Logic Design Flip-flops.

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Presentation transcript:

Introduction to Sequential Logic Design Flip-flops

2 Prev… Latches  S-R  S-bar-R-bar  S-R with enable signal  D

3 FF vs. Latch Latches and flip-flops (FFs) are the basic building blocks of sequential circuits.  latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs, independent of a clocking signal.  flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.

4 Edge triggered D Flip-Flop A D FF combines a pair of D latches. Master/slave D FF  Positive-edge-triggered D FF  Negative-edge-triggered D FF  Edge-Triggered D FF with Enable  Scan FF

5 Positive-Edge-triggered D flip-flop

6 Dynamic-input indicator

7 Edge-triggered D flip-flop behavior

8

9

10 D flip-flop timing parameters Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK)

11 D FF with asynchronous inputs Force the D FF to a particular state independent of the CLK and D inputs. PR (Preset) and CLR (Clear)

12 Negative-edge triggered D FF Simply inverts the clock input. Active low.

13 Negative-edge triggered D FF Simply inverts the clock input. Active low.

14 J-K flip-flops

15 T (toggle) flip-flops A T FF changes state on every tick of the clock. (be toggled on every tick) Q has precisely half the frequency of the T. Important for counters Positive-edge-triggered T FF How to build T FF using J-K FF and D FF?

16 T (toggle) flip-flops with enable How to build a T FF with enable using?  D FF  J-K FF

17 T (toggle) flip-flops with enable

18 Next… FSM analysis Read Ch-7.3