Gheorghe M. Ştefan

Register file 2014Digital Integrated Circuits - week eight2 Let us go back to the slide 16 form Week 5: bwand : regFile[destAddr] <= regFile[leftAddr] & regFile[rightAddr];

2014Digital Integrated Circuits - week eight3 Reading is asynchronous 3-port memory: Where goes destAddr ? How can be read two distinct locations?

FPGA: Field Programmable Gate Array 2014Digital Integrated Circuits - week eight4

I/O : input-output interface 2014Digital Integrated Circuits - week eight5 For non-inverting tristae buffer see week 4 slide 3

Switch matrix 2014Digital Integrated Circuits - week eight6

CLB : configurable logic block 2014Digital Integrated Circuits - week eight7

BS : bit slice 2014Digital Integrated Circuits - week eight8

Second-order systems: automata Asynchronous automata Synchronous automata 2014Digital Integrated Circuits - week eight9

Example of asynchronous automaton: D-FF as 2-OS 2014Digital Integrated Circuits - week eight10 (x,y,z) : for switching in 1 [x,y,z] : for switching in 0 x : value in set-up time y : value in hold time z : possible value after hold time

Two-state automata One-input 2-state automaton: the T flip-flop T = 0 : no operation T = 1 : switch Function: one-bit counter 2014Digital Integrated Circuits - week eight11

The structure of TF-F 2014Digital Integrated Circuits - week eight12 XOR : enabled one-bit increment circuit T=1 enables the increment For T = 1 the behavior is autonomous

Two-state automata (cont) Two-input 2-state automaton: the JK flip-flop J = 0, K = 0 : no operation J = 0, K = 1 : reset J = 1, K = 0 : set J = 1, K = 1 : switch For J = 0, K = 1 the behavior is autonomous 2014Digital Integrated Circuits - week eight13

Functional, simple automaton: the Counter TF-F is the elementary, 1-bit, counter with T = INC The recursive definition of the n-bit counter COUNT n S COUNT (n) = O(n 2 ) S COUNT (n) = O(n 2 ) S COUNT (n) = O(n 2 ) T COUNT (n) = O(log n) 2014Digital Integrated Circuits - week eight14

The full counter 2014Digital Integrated Circuits - week eight15

Finite, complex automata 2014Digital Integrated Circuits - week eight16 A = (X, Y, Q, f, g) X  {0,1} n is the n-bit coded input set Y  {0,1} m is the m-bit coded output set Q  {0,1} s is the s-bit coded internal state (state) set f:(X × Q) → Q the state transition function g:(X × Q) → Y the output transition function for Mealy version g:(Q) → Y the output transition function for Moore version What is the difference from the general definition of a digital system?

Half-automaton: A 1/2 = (X, Q, f) Finite automaton A is a complex circuit: C A  O(|Q|) Initial state: a state without predecessor. Initial automaton: Q’  Q Strict initial automaton: Q’= {q 0 }, A = (X, Y, Q, f, g; q 0 ) Delayed automaton: the output goes through a register Output with no delay: y(t) = g(x(t), q(t)) for Mealy automaton One clock cycle delay: y(t) = g(x(t-1), q(t-1)) for delayed Mealy automaton y(t) = g(q(t)) = g(f(x(t-1), q(t-1))) for Moore automaton Two clock cycles delay: y(t) = g(q(t-1)) = g(f(x(t-2), q(t-2))) for delayed Moore automaton 2014Digital Integrated Circuits - week eight17

Representing finite automata Half-automaton for bb detection in streams belonging to {a,b} n 2014Digital Integrated Circuits - week eight18

Moore version: 2014Digital Integrated Circuits - week eight19

Mealy version: 2014Digital Integrated Circuits - week eight20

Home work 8 Problem 1: a) Draw an 4-bit counter according to the slides 14 and 12 using DF-Fs, XORs and AND gates b) Emphasize the structure of the increment circuit in the resulting structure Problem 2: a) Define the graph of the finite automaton used to recognize by its final state the sequence abba in a stream of symbols belonging to {a,b,c} n. b) Define the associated flow-chart for the two inputs bits X 0 and X 1 coded as follows: a = 00 b = 01 c = Digital Integrated Circuits - week eight21