Technical University Tallinn, ESTONIA 1 Boolean derivatives Calculation of the Boolean derivative: Given:

Technical University Tallinn, ESTONIA 2 Derivatives for complex functions Boolean derivative for a complex function: Example: Additional condition:

Technical University Tallinn, ESTONIA 3 Boolean differentials and fault diagnosis x 1 = 0 x 2 = 1 x 3 = 1 dy = 0 Correct output signal : x 1 = 0 x 2 = 0 x 3 = 0 dy = 1 Erroneous output signal :

Technical University Tallinn, ESTONIA 4 Boolean differentials and fault diagnosis Rule: = 0 Diagnosis: The line x 3 works correct There is a fault: The fault is missing

Technical University Tallinn, ESTONIA 5 Binary Decision Diagrams Functional synthesis BDDs: Shannon’s Theorem: xkxk y x1x1 y x2x2 x3x3 x4x4 x3x3 x4x4 Using the Theorem for BDD synthesis: Example:

Technical University Tallinn, ESTONIA 6 Binary Decision Diagrams D C qc q’ D S C q Elementary BDDs R c q’ S R q’q’ R U D Flip-Flop RS Flip-Flop JK Flip-Flop S J q R c q’ S R q’q’ C K K J U - unknown value

Technical University Tallinn, ESTONIA 7 Building a SSBDD for a Circuit & 1 1 x1x1 x2x2 x3x3 x 21 x 22 y a b a b y a x1x1 x 21 b x 22 x3x3 a y x3x3 y x3x3 x1x1 x 21 DD-library: Superposition of DDs  Superposition of Boolean functions: Given circuit: Compare to SSBDD Structurally Synthesized BDDs: ba

Technical University Tallinn, ESTONIA 8 High-Level DDs for Finite State Machines State Transition Diagram: DD:

Technical University Tallinn, ESTONIA 9 High-Level Decision Diagrams y 4 y 3 y 1 R 1 + R 2 IN + R 2 R 1 * R 2 IN* R 2 y 2 R  0 R 2 IN R Superposition of High-Level DDs: A single DD for a subcircuit R2R2 R 2 + M 3 Instead of simulating all the components in the circuit, only a single path in the DD should be traced M1M1 M2M2

Technical University Tallinn, ESTONIA 10 Decision Diagrams for Microprocessors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  A I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A High-Level DDs for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

Technical University Tallinn, ESTONIA 11 Mapping Transistor Faults to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Test calculation by Boolean derivative: Generic function with defect: Function: Faulty function:

Technical University Tallinn, ESTONIA 12 Functional Fault Model Example: x1x1 x2x2 x3x3 y & & x1x1 x2x2 x3x3 y & & & Equivalent faulty circuit: Bridging fault causes a feedback loop: Sequential constraints: A short between leads x k and x l changes the combinational circuit into sequential one t x 1 x 2 x 3 y

Technical University Tallinn, ESTONIA 13 Structural Test Generation Structural gate-level testing: Path activation & & & & & & & a b c d e y Macro D D D D D Fault sensitisation: x 7,1 = D Fault propagation: x 2 = 1, x 1 = 1, b = 1, c = 1 Line justification: x 7 = D = 0: x 3 = 1, x 4 = 1 b = 1: (already justified) c = 1: (already justified) Symbolic fault modeling: D = 0 - if fault is missing D = 1 - if fault is present Test pattern

Technical University Tallinn, ESTONIA 14 Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y Testing Stuck-at-1 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 21  1, x 31  1, x 13  0 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x

Technical University Tallinn, ESTONIA 15 Example: Test Generation with BDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y D D Testing Stuck-at faults on inputs: Test pair D=0,1: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 1  0, x 1  1 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x x1x1 y x2x2 x4x4 x3x3 x2x2 SSBDD: BDD:

Technical University Tallinn, ESTONIA 16 Test generation Test generation by using disjunctive normal forms

Technical University Tallinn, ESTONIA 17 Multiple Fault Testing To test a path under condition of multiple faults, two pattern test is needed As the result, either the faults on the path under test are detected or the masking fault is detected Example: The lower path from b to output is under test A pair of patterns is applied on b There is a masking fault c  1 1st pattern: fault on b is masked 2nd pattern: fault on c is detected  &  & 10  11 11(00) 10 (11) (00) a b c d Testing multiple faults by pairs of patterns The possible results: 01 - No faults detected 00 - Either b  0 or c  1 detected 11 - The fault b  1 is detected  1 faults (11)

Technical University Tallinn, ESTONIA 18 Delay Faults Two models: - gate delay - path delay Test pattern pairs: The first test initializes the circuit, and the second pattern sensitizes the fault Robust delay test : If and only if when L is faulty and a test pair is applied, the fault is detected independently of the delays along the path & & & 1 & A D C B x1x1 x2x2 x3x xxx0 1x0 0xxxx1 1 Delay fault activated, but not detected & & & 00 & A D C B x1x1 x2x2 x3x xxx1 11 1xxxx0 0xxxxx1 Robust delay test y y

Technical University Tallinn, ESTONIA 19 Test Generation I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  IA I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A Test program generation for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A IN 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

Technical University Tallinn, ESTONIA 20 Test Generation Test program generation for a microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A IN 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Scanning test for adder: Instruction sequence I 5 I 1 I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load

Technical University Tallinn, ESTONIA 21 Test Generation Test program generation for a microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A IN 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Conformity test for decoder: Instruction sequence I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN Data generation: Data IN,A,R are generated so that the values of all functions were different

Technical University Tallinn, ESTONIA 22 Deductive Fault Simulation & & a c b y Fault list calculation: L a = L 4  L 5 L b = L 1  L 2 L c = L 3  L a L y = L b - L c L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Gate-level fault list propagation L a – faults causing erroneous signal on the node a L y – faults causing erroneous signal on the output node y Library of formulas for gates

Technical University Tallinn, ESTONIA 23 Deductive Fault Simulation & & a c b y Fault list calculated: L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Solving Boolean differential equation: Macro-level fault propagation:  L k

Technical University Tallinn, ESTONIA 24 Critical Path Tracing & & a c b y y Problems : & & /1 y & & y 1/ The critical path is not continuous The critical path breaks on the fan-out

Technical University Tallinn, ESTONIA 25 Parallel Critical Path Tracing & 1 x1x1 y Detected faults vector: T1: No faults detected T2: x 1  1 detected T3: x 1  0 detected T4: No faults detected x3x3 x2x2 Handling of fanout points: Fault simulation Boolean differential calculus x y xkxk x2x2 x1x1 F

Technical University Tallinn, ESTONIA 26 Combinational Fault diagnosis 0110 T FaultF 5 located FaultsF 1 andF 4 are not distinguishable Fault localization by fault tables No match, diagnosis not possible

Technical University Tallinn, ESTONIA 27 Combinational Fault Diagnosis To reduce the cost of building a fault table, the detected faults may be dropped from simulation All the faults detected for the first time by the same vector produce the same column vector in the table, and will included in the same equivalence class of faults Testing can stop after the first failing test, no information from the following tests can be used Minimization of diagnostic data With fault dropping, only 19 faults need to be simulated compared to the all 42 faults The following faults remain not distinguishable: {F 2, F 3 }, {F 1, F 4 }. A tradeoff between computing time and diagnostic resolution can be achieved by dropping faults after k >1 detections

Technical University Tallinn, ESTONIA 28 Improving Diagnostic Resolution Method: F1 may influence both outputs, F2 may influence only x 8 A test pattern 0010 activates F1 up to the both outputs, and F2 only to x 8 If both outputs will be wrong, F1 is present, and if only x 8 will be wrong, F2 is present Generating tests to distinguish faults F1: x 3,1  0 Faults are influencing on different outputs: x 2 x 3 x 4 x 3,1 x 3,2 x 5 x 6 x 7 x  1 x F2: x 4  1

Technical University Tallinn, ESTONIA 29 Improving Diagnostic Resolution Method: Both faults influence the same output of the circuit One of them should be blocked Two possibilities: A test pattern 0100 activates the fault F2. F1 is not activated: the line x 3,2 has the same value as it would have if F1 were present A test pattern 0110 activates the fault F2. F1 is now activated at his site but not propagated through the AND gate Generating tests to distinguish faults F1: x 3,2  0 F2: x 5,2  1 How to activate a fault without activating another one? x 5,1 x 5,2 x 2 x 3 x 4 x 3,1 x 3,2 x 5 x 6 x 7 x  1 x /1 0

Technical University Tallinn, ESTONIA 30 Sequential Fault Diagnosis Sequential fault diagnosis by Edge-Pin Testing Two faults F 1,F 4 remain indistinguishable Not all test patterns used in the fault table are needed Different faults need for identifying test sequences with different lengths The shortest test contains two patterns, the longest four patterns Diagnostic tree:

Technical University Tallinn, ESTONIA 31 Sequential Fault Diagnosis Guided-probe testing at the gate level Searh tree: Faulty circuit

Technical University Tallinn, ESTONIA 32 Sequential Fault Diagnosis Guided-probe testing at the macro-level & & & & & & & a b c d e y Macro y 0 1 There is a fault on the line 7 1 Nodes to be pinpointed: Gate level: c, e, d, 1, a, 7 1 (6 attempts) Macro level (DD): 1, 7 1 (2 attempts) Rules on DDs: Only the nodes where the leaving direction coincides with the leaving direction from the DD should be pinponted If simulation shows that these nodes cannot explain the faulty behavior they can be dropped 0 1