04/04/20071 Image Understanding Architecture: Exploiting Potential Parallelism in Machine Vision

04/04/20072 Overview Heterogeneous parallel processor –Three distinct layers Meet the real-time computational requirements of computer vision systems Exploit the various forms of parallelism within a computer vision algorithm suite –Data parallelism –Control parallelism Collaborative effort –University of Massachusetts, Amhurst (UMASS) –Hughes Research Laboratory Circa 1980’s –Part of the DARPA image understanding research initiative

04/04/20073 Background What is computer vision? Process images (or streams of images) with the intent of –Object recognition –Vehicle guidance –Manufacturing –etc. Create a system that extracts information (not just data) from a picture

04/04/20074 An Image (as we see it)

04/04/20075 Mechanization of Processing

04/04/ An Image (as the computer sees it)

04/04/20077 What gets processed? Gradients (edges) Color Transformations –Rotation –Translation –Stretching Texture Shading Shape Context All of these are based on searching for patterns in the image colors

04/04/20078 How should a computer process visual scenes? As it turns out, mimicking a biological system in circuits and software is extremely difficult –Cameras are not as sophisticated as the eye –Processors/software are not as sophisticated as the brain

04/04/20079 How should a computer process visual scenes? Preprocessing –Image conditioning (number crunching) Low Level Vision –Feature extraction (number crunching) Mid Level Vision –Feature description (symbolic processing) High Level Vision –Object recognition (advanced data structures)

04/04/ Three distinct “levels” Data intensive –Preprocessing –Low Level Vision Semi-data intensive, semi-control intensive –Mid Level Vision Control intensive –High Level Vision

04/04/ How do we process visual scenes? Preprocessing –Image conditioning Low Level Vision –Feature extraction Mid Level Vision –Feature description High Level Vision –Object recognition R1 R2 R3 G1 Intersects(70) Intersects(40) Bounds

04/04/ Basic Philosophy Create a computer comprised of three architectures, each suited to one of the levels of a computer vision application Heterogeneous architecture –Multiple types of processing elements –Multiple interconnect topologies –Multiple programming languages

04/04/ The Architecture

04/04/ The Architecture Content Addressable Array Parallel Processor (CAAPP) –SIMD –Configurable into separate groups Intermediate Communication Associative Processor (ICAP) –MIMD –SPMD (Single Program Multiple Data) All PEs have the same program but each has it’s own program counter (Asynchronous SIMD) Symbolic Processing Array (SPA) –MIMD

04/04/ CAAPP Bit-serial processors ALU 320 bits of cache 32KBits of main memory Instructions come “from above” –Array Control Unit (ACU) Communication –Configurable mesh – coterie network –A “coterie” is a group of PEs that work [somewhat] independently (still only 1 instruction stream)

04/04/ ICAP Digital Signal Processor (DSP) –Specialty architecture for performing numerical transforms 320 bits of cache 256KBytes of main memory (128K program, 128K data) Communication –Cross-bar switch

04/04/ SPA Not fully specified –Commercially available multi-processor –Networked workstations

04/04/ CAAPP to ICAP Communication One ICAP PE is responsible for (communicates with) 64 CAAPP PEs (8 x 8 mesh) Communication is via a dual-port [shared] memory

04/04/ ICAP to SPA Communication One SPA PE is responsible for (communicates with) 64 ICAP PEs (8 x 8 mesh) Communication is via a dual-port [shared] memory

04/04/ Full System Specification 64 SPA PEs –MIMD –RISC processing architecture 4K ICAP PEs (64 x 64) –MIMD/SPMD –Digital Signal Processor (DSP) 256K CAAPP PEs (512 x 512) –SIMD –1-bit processing architecture

04/04/ st Generation Proof of concept –4096 CAAPP processors (64 x 64) –64 ICAP processors –1 SPA processor CAAPP chip ICAP board System chasis

04/04/ nd Generation 1/16 th of a full scale system –16K CAAPP processors –64 ICAP processors Commercial chips – TI TMS320C40 32-bit processor Communication is token-ring over 2 x 2 meshes plus inter-processor DMA channels –4 SPA processors Networked workstations

04/04/ nd Generation CAAPP chip ICAP board ICAP communcation topology

04/04/ Programming Required writing separate code for each level In the beginning there were 3 different programming languages involved –Forth, C, Assembly Plan was to move to C/C++/Lisp with parallel extensions (class libraries) –Ada was planned Goal was to develop a single language compiler for the entire system

04/04/ Interesting Bits This group actually started from the problem specification and set out to build an architecture to support it –Contrary to other parallel processor developments of the time Programming proved very difficult –Require intimate knowledge of architecture (especially the coterie network) and algorithms –A simulator of the full system existed for program development, research

04/04/ End Notes Emphasis was on –Proof of concept –Mapping algorithms to the architecture –Fabricating chips Cancelled 1995 –Various chips/board fabricated and tested –Various software components developed and tested