Programmable Logic Circuits: Multipliers Dr. Eng. Amr T. Abdel-Hamid ELECT 90X Fall 2009 Slides based on slides prepared by: B. Parhami, Computer Arithmetic: Algorithms and Hardware Design, Oxford University Press, I. Koren, Computer Arithmetic Algorithms, 2nd Edition, A.K. Peters, Natick, MA, 2002.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Shift/Add Multiplication Algorithms Notation for our discussion of multiplication algorithms: aMultiplicand a k–1 a k–2... a 1 a 0 xMultiplier x k–1 x k–2... x 1 x 0 p Product (a  x)p 2k–1 p 2k–2... p 3 p 2 p 1 p 0 Initially, we assume unsigned operands Multiplication of two 4-bit unsigned binary numbers in dot notation.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Preferred Multiplication Recurrence Multiplication with right shifts: top-to-bottom accumulation p (j+1) =(p (j) + x j a 2 k ) 2 –1 withp (0) = 0and |–––add–––|p (k) = p = ax + p (0) 2 –k |––shift right––| Multiplication with left shifts: bottom-to-top accumulation p (j+1) = 2 p (j) + x k–j–1 a withp (0) = 0and |shift|p (k) = p = ax + p (0) 2 k |––––add––––|

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Examples of Basic Multiplication Examples of sequential multiplicati on with right and left shifts. Right-shift algorithm Left-shift algorithm =============================================== a a x x =============================================== p (0) x 0 a p (0) –––––––––––––––––––––––––+x 3 a p (1) –––––––––––––––––––––––– p (1) p (1) x 1 a p (1) –––––––––––––––––––––––––+x 2 a p (2) –––––––––––––––––––––––– p (2) p (2) x 2 a p (2) –––––––––––––––––––––––––+x 1 a p (3) –––––––––––––––––––––––– p (3) p (3) x 3 a p (3) –––––––––––––––––––––––––+x 0 a p (4) –––––––––––––––––––––––– p (4) p (4) ===============================================

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Basic Hardware Multipliers Hardware realization of the sequential multiplication algorithm with additions and right shifts.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Multiplication of Signed Numbers Sequential multiplication of 2’s-complement numbers with right shifts (positive multiplier). ============================ a x ============================ p (0) x 0 a ––––––––––––––––––––––––––––– 2p (1) p (1) x 1 a ––––––––––––––––––––––––––––– 2p (2) p (2) x 2 a ––––––––––––––––––––––––––––– 2p (3) p (3) x 3 a ––––––––––––––––––––––––––––– 2p (4) p (4) x 4 a ––––––––––––––––––––––––––––– 2p (5) p (5) ============================ Negative multiplicand, positive multiplier: No change, other than looking out for proper sign extension

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits The Case of a Neg ative Multiplier Sequential multiplication of 2’s-complement numbers with right shifts (negative multiplier). ============================ a x ============================ p (0) x 0 a ––––––––––––––––––––––––––––– 2p (1) p (1) x 1 a ––––––––––––––––––––––––––––– 2p (2) p (2) x 2 a ––––––––––––––––––––––––––––– 2p (3) p (3) x 3 a ––––––––––––––––––––––––––––– 2p (4) p (4) (  x 4 a) ––––––––––––––––––––––––––––– 2p (5) p (5) ============================ Negative multiplicand, negative multiplier: In last step (the sign bit), subtract rather than add

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Booth’s Encoding  Recall grade school trick  When multiplying by 9:  Multiply by 10 (easy, just shift digits left)  Subtract once  E.g.  x 9 = x (10 – 1) = –  Converts addition of six partial products to one shift and one subtraction  Booth’s algorithm applies same principle  Except no ‘9’ in binary, just ‘1’ and ‘0’  So, it’s actually easier!

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Booth’s Encoding  Search for a run of ‘1’ bits in the multiplier  E.g. ‘0110’ has a run of 2 ‘1’ bits in the middle  Multiplying by ‘0110’ (6 in decimal) is equivale nt to multiplying by 8 and subtracting twice, si nce 6 x m = (8 – 2) x m = 8m – 2m  Hence, iterate right to left and:  Subtract multiplicand from product at first ‘1’  Add multiplicand to product after first ‘1’  Don’t do either for ‘1’ bits in the middle

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Booth’s Algorithm Curren t bit Bit to right ExplanationExampleOperation 10Begins run of ‘1’ Subtract 11Middle of run of ‘1’ Nothing 01End of a run of ‘1’ Add 00Middle of a run of ‘0’ Nothing

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits 11 Booth’s Encoding  Really just a new way to encode numbers  Normally positionally weighted as 2 n  With Booth, each position has a sign bit  Can be extended to multiple bits 0110Binary bit Booth bit Booth

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Booth’s Recoding Radix-2 Booth’s recoding ––––––––––––––––––––––––––––––––––––– x i x i–1 y i Explanation ––––––––––––––––––––––––––––––––––––– 0 0 0No string of 1s in sight 0 1 1End of string of 1s in x 1 0  1Beginning of string of 1s in x 1 1 0Continuation of string of 1s in x ––––––––––––––––––––––––––––––––––––– Example Operand x (1)    1 1   1 0 Recoded version y Justification 2 j + 2 j– i i = 2 j+1 – 2 i

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Example Multiplication with Booth’s Recoding Sequential multiplication of 2’s-complement numbers with right shifts by means of Booth’s recoding. ============================ a x Multiplier y  1 1  1 1  1 Booth-recoded ============================ p (0) y 0 a ––––––––––––––––––––––––––––– 2p (1) p (1) y 1 a ––––––––––––––––––––––––––––– 2p (2) p (2) y 2 a ––––––––––––––––––––––––––––– 2p (3) p (3) y 3 a ––––––––––––––––––––––––––––– 2p (4) p (4) y 4 a ––––––––––––––––––––––––––––– 2p (5) p (5) ============================ –––––––––– x i x i–1 y i ––––––––––  ––––––––––

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Radix-4 Multiplication in Dot Notation Number of cycles is halved, but now the “difficult” multiple 3a must be dealt with Radix-4, or two-bit- at-a-time, multiplication in dot notation

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits A Possible Design for a Radix-4 Multiplier Precomputed via shift-and-add (3a = 2a + a) k + 1 cycles, rather than k One extra cycle not too bad, but we would like to avoid it if possible Solving this problem for radix 4 may also help when dealing with even higher radices The multiple generation part of a radix-4 multiplier with precomputation of 3a.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Example Radix-4 Multiplication Using 3a ================================ a a x ================================ p (0) (x 1 x 0 ) two a ––––––––––––––––––––––––––––––––– 4p (1) p (1) (x 3 x 2 ) two a ––––––––––––––––––––––––––––––––– 4p (2) p (2) ================================ Example of radix-4 multiplication using the 3a multiple.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Modified Booth’s Recoding Radix-4 Booth’s recoding yielding (z k/2... z 1 z 0 ) four ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– x i+1 x i x i–1 y i+1 y i z i/2 Explanation ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– No string of 1s in sight End of string of 1s Isolated End of string of 1s  1 0  2Beginning of string of 1s  1 1  1End a string, begin new one  1  1Beginning of string of 1s Continuation of string of 1s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– (1)  2 2  1 2  1  1 0  2 Radix-4 version z Context Recoded radix-2 digits Radix-4 digit Example Operand x (1)    1 1   1 0 Recoded version y

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Example Multiplication via Modified Booth’s Recoding ================================ a x z  1  2 Radix-4 ================================ p (0) z 0 a ––––––––––––––––––––––––––––––––– 4p (1) p (1) z 1 a ––––––––––––––––––––––––––––––––– 4p (2) p (2) ================================ Example of radix-4 multiplication with modified Booth’s recoding of the 2’s- complement multiplier.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Multiple Generation with Radix-4 Booth’s Recoding The multiple generation part of a radix-4 multiplier based on Booth’s recoding. Sign extension, not 0

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits On an average no improvement in speed Count = 4 Vs 8 speed improvement Count = 7 Vs 9 no speed improvement Count = 16 Vs 8 speed worsened.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Yet Another Design for Radix-4 Multiplication Radix-4 multiplication with two carry-save adders.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Radix-8 and Radix-16 Multipliers Radix-16 multiplication with the upper half of the cumulative partial product in carry-save form. 4-bit right shift

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits A Spectrum of Multiplier Design Choices High-radix multipliers as intermediate between sequential radix-2 and full-tree multipliers.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Multibeat Multipliers Observation: Half of the clock cycle goes to waste Conceptual view of a twin-beat multiplier. One cycle Begin changing FF contents Change becomes visible at FF output

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Twin-Beat and Three-Beat Multipliers Twin-beat multiplier with radix-8 Booth’s recoding.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Full-Tree Multipliers General structure of a full-tree multiplier.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Full-Tree versus Partial-Tree Multiplier Schematic diagrams for full-tree and partial-tree multipliers.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Variations in Full-Tree Multiplier Design Designs are distinguished by variations in three elements: 2. Partial products reduction tree 3. Redundant-to-binary converter 1. Multiple-forming circuits

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Example of Variations in CSA Tree Design Two different binary 4  4 tree multipliers.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Binary Tree of 4-to-2 Reduction Modules Due to its recursive structure, a binary tree is more regular than a 3-to-2 reduction tree when laid out in VLSI Tree multiplier with a more regular structure based on 4-to-2 reduction modules.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Array Multipliers A basic array multiplier uses a one-sided CSA tree and a ripple- carry adder. Details of a 5  5 array multiplier using FA blocks.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Array Multiplier Built of Modified Full-Adder Cells Design of a 5  5 array multiplier with two additive inputs and full-adder blocks that include AND gates. FA

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Pipelined Array Multipliers With latches after every FA level, the maximum throughput is achieved Latches may be inserted after every h FA levels for an intermediate design Pipelined 5   5 array multiplier using latched FA blocks. The small shaded boxes are latches. Example: 3-stage pipeline

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Bit-Serial Multipliers What goes inside the box to make a bit-serial multiplier? Can the circuit be designed to support a high clock rate? FA FF Bit-serial adder (LSB first) x0x0 y0y0 s0s0 x1x1 y1y1 s1s1 x2x2 y2y2 s2s2 … … … Bit-serial multiplier a0a0 x0x0 p0p0 a1a1 x1x1 p1p1 a2a2 x2x2 p2p2 … … … (Must follow the k-bit inputs with k 0s; alternatively, view the product as being only k bits wide) ?

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Semisystolic Serial-Parallel Multiplier Semi-systolic circuit for 4  4 multiplication in 8 clock cycles. This is called “semisystolic” because it has a large signal fan-out of k (k-way broadcasting) and a long wire spanning all k positions

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Systolic Retiming as a Design Tool Example of retiming by delaying the inputs to C L and advancing the outputs from C L by d units A semisystolic circuit can be converted to a systolic circuit via retiming, which involves advancing and retarding signals by means of delay removal and delay insertion in such a way that the relative timings of various parts are unaffected

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits A First Attempt at Retiming A retimed version of our semi- systolic multiplier.

Dr. Amr Talaat ELECT 90X Programmable Logic Circuits Deriving a Fully S ystolic Multiplier A retimed version of our semi- systolic multiplier.