Michal Szelezniak – LBL-IPHC meeting – May 2007 Cluster finder in the HFT readout Single-hit detection efficiency for a cluster-finder algorithm implemented in the readout chain of the HFT

Michal Szelezniak - LBL-IPHC meeting May Goals and tools Goals: – estimate the single-hit detection efficiency and fake-hit rate as a function of different threshold criteria Cut on signal in the central pixel (high cut) Cut on ONE of the EIGHT neighbors (low cut) – Compare results with the classical cluster finder based on two cuts: Cut on S/N for the central pixel Cut on Sum of S/N for the crown Tools: – Simulations based on data from the beam test runs with MimoStar2 chips taken at DESY in summer 2006 Chip 6, Rad-tol diode, 20 deg C, 4 MHz readout clock, run (no beam) and 14546

Michal Szelezniak - LBL-IPHC meeting May Simulations Frames 15x15 pixels created from available noise samples Real clusters (5x5 pixels) embedded into centers of frames Total number of frames: 7588

Michal Szelezniak - LBL-IPHC meeting May Definitions ● N org – number of clusters detected in the original central 5x5 regions of all entry events, ● N TOT – the total number of clusters embedded in the central regions of entry events equal to the number of frames (N FRAMES =7588). ● N F – number of fake clusters, ● n det – number of clusters detected in one frame, ● n org – number of clusters detected in one frame at the position where the original cluster was embedded, ● N PIX =160 – number of pixels in one frame that are scanned for clusters, excluding the original cluster of 25 pixels (in addition, two rows at the edges of each frame where not scanned).

Michal Szelezniak - LBL-IPHC meeting May Processing

Michal Szelezniak - LBL-IPHC meeting May Cluster size and pointing accuracy

Michal Szelezniak - LBL-IPHC meeting May Comparison of algorithms

Michal Szelezniak - LBL-IPHC meeting May Comparison of algorithms

Michal Szelezniak - LBL-IPHC meeting May Conclusions Satisfactory performance for a range of cuts Much simpler algorithm than the classical one – simpler for hardware implementation (FPGA, on- chip (?) - requires much less resources) Binary readout gives a pretty good performance, but there is no security margin and the cut has to be precisely adjusted for a high efficiency and low accidental rate