ASIC Design Final project requirement - 1 Mid-term project requirement –Write a complete spec of MSDAP Introduce the application Analyze the application.

Slides:

Advertisements

Similar presentations

HDL Programming Fundamentals

Advertisements

The Systems Analysis Toolkit

ECE 272 Xilinx Tutorial. Workshop Goals Learn how to use Xilinx to: Draw a schematic Create a symbol Generate a testbench Simulate your circuit.

Procedural Writing Writing a How-To Paper.

1 Lecture 1: Verilog HDL Introduction. 2 What is Verilog HDL? Verilog Hardware Description Language(HDL)? –A high-level computer language can model, represent.

State Diagram. What is State Diagram?  State diagram is used to show the state space of a given class, the events that cause a transition from one state.

1 Spring 2007 CSCI 660 CSCI-660 Project Title Project team members’ names.

EE694v-Verification-Lect5-1- Lecture 5 - Verification Tools Automation improves the efficiency and reliability of the verification process Some tools,

Final project requirement

FIGURE 1-1 A Computer System

1 Objective of today’s lesson S oftware engineering occurs as a consequence of a process called system engineering. Instead of concentrating solely on.

Prof. D. Zhou UT Dallas Analog Circuits Design Automation 1.

Introduction to High-Level Language Programming

CAES1507 Professional and Technical Written Communication for Engineers Session Six Theory and Design.

Your User Name is the first portion of your Carleton Connect account eg. mroger4 if the was n.ca

CS 103 Discrete Structures Lecture 01 Introduction to the Course

TECHNICAL WRITING October 31 st, With a partner Write simple “step-by-step” instructions for sending a Kakao Talk message with a phone.

ASIC/FPGA design flow. FPGA Design Flow Detailed (RTL) Design Detailed (RTL) Design Ideas (Specifications) Design Ideas (Specifications) Device Programming.

Configuration Management (CM)

TECHNICAL WRITING October 27, Instructions and Procedures Instructions explain how to perform a task in a step-by-step manner. They vary in length,

Free yourself from fear and attempt the impossible.

EL 3101 EL310 Hardware Description Languages Spring 2015 Instructor: Ilker Hamzaoglu Teaching Assistant: Ercan Kalalı Web Site:

Teaching Functional Verification – Course Organization Design Automation Conference Sunday, June 9, 2002.

Galen SasakiEE 260 University of Hawaii1 Electronic Design Automation (EDA) EE 260 University of Hawaii.

ECE 449: Computer Design Lab Coordinator: Kris Gaj TAs: Tuesday session: Pawel Chodowiec Thursday session: Nghi Nguyen.

SUPERCOMPUTING CHALLENGE KICKOFF 2015 A Model for Computational Science Investigations Oct 2015 © challenge.org Supercomputing Around.

The Macro Design Process The Issues 1. Overview of IP Design 2. Key Features 3. Planning and Specification 4. Macro Design and Verification 5. Soft Macro.

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Logic Design Process n Functional/ Non-functional requirements n Mapping into an FPGA n Hardware.

ECE 545 Project 2 Specification. Project 2 (15 points) – due Tuesday, December 19, noon Application: cryptography OR digital signal processing optimized.

Computer Engineering 1502 Advanced Digital Design Professor Donald Chiarulli Computer Science Dept Sennott Square

Connecting with Computer Science2 Objectives Learn how software engineering is used to create applications Learn some of the different software engineering.

GET CONNECTED Information Technology Career Cluster.

CS680: Announcements and Feedbacks Sung-Eui Yoon ( 윤성의 ) Course URL:

Introduction to Computer Architecture

ELEE 4303 Digital II Introduction to Verilog. ELEE 4303 Digital II Learning Objectives Get familiar with background of HDLs Basic concepts of Verilog.

Mark Dixon 1 Tech – Final Report. Mark Dixon 2 Aims & Objectives Give guidance on: –Project Report –Demonstration.

Dual Logo Procedures Alex Zamfirescu IEC USNC TA TC93 Convener IEC TC93 WG2 November 2004.

Digital Design Using VHDL and PLDs ECOM 4311 Digital System Design Chapter 1.

CDA 4253 FPGA System Design Hao Zheng Dept of Comp Sci & Eng USF.

Implementation Of The (COVE) ELECTRONIC PROOF OF VALUE.

EE694v - Verification - Lect Lect 12,13,14 – 762 Testbenches Lets look at the EE 762 testbenches Look at stimulus generation techniques Look at response.

Simple ALU How to perform this C language integer operation in the computer C=A+B; ? The arithmetic/logic unit (ALU) of a processor performs integer arithmetic.

Rohini Ravichandran Kaushik Narayanan A MINI STEREO DIGITAL AUDIO PROCESSOR (BEHAVIORAL MODEL)

Prof. D. Zhou UT Dallas Analog Circuits Design Automation 1.

Teaching Functional Verification – Course Organization Design Automation Conference Sunday, June 9, 2002.

CS122 – Quiz 2 Winter, 2013 Quiz Hints. Quiz 2 Hints Question 1 – working with the “if” statement  First, we did not fully explain the structure of the.

UNIT 1 ROUTERS Cambridge Technicals. Routers You need to explain the function of a ROUTER in how computers connect to the internet and to networks in.

ASIC/FPGA design flow. Design Flow Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation.

Program Design. Simple Program Design, Fourth Edition Chapter 1 2 Objectives In this chapter you will be able to: Describe the steps in the program development.

1 Lecture 1: Verilog HDL Introduction. 2 What is Verilog HDL? Verilog Hardware Description Language(HDL)? –A high-level computer language can model, represent.

1 A hardware description language is a computer language that is used to describe hardware. Two HDLs are widely used Verilog HDL VHDL (Very High Speed.

EE694v - Verification - Lect 12

Introduction to Computing

ASIC Design Methodology

IEC TC93 Liaison Report to DASC Alex Zamfirescu IEC USNC TA TC93 Convener IEC TC93 WG2 September 2004.

Figure 1.1 The Altera UP 1 CPLD development board.

ACT Writing: How To.

Logic and Computer Design Fundamentals

Introduction to Computers

Digital Engineering Laboratory

Computer Architecture

HDL Hardware Description Language

Teaching Functional Verification – Course Organization

Implementing Combinational

What is Science? Review This slide show will present a question, followed by a slide with an acceptable answer. For some questions, there is a definite.

ECE 554 Digital Engineering Laboratory Nam Sung Kim (Chunhua Yao –TA)

CS 153 Logic Design Lab Professor Ian G. Harris

Digital Engineering Laboratory

Homework 2 Degree of Freedom

Mathematics Unit 30: Shapes

Presentation transcript:

ASIC Design Final project requirement - 1 Mid-term project requirement –Write a complete spec of MSDAP Introduce the application Analyze the application in terms of operation and I/O requirements Explain the particular computation method Describe the procedure of developing a spec Develop a complete spec of MSDAP

ASIC Design Final project requirement - 2 –Develop a behavior model of MSDAP based on the spec The behavior model needs to be written in VHDL (or Verilog with the permission of TA) The model should cover the complete spec requirement

ASIC Design Final project requirement - 3 –Develop a testbench of MSDAP Write a testbench based on the spec in VHDL (or Verilog with the permission of TA) The testbench is the behavior model of the “host machine” discussed in the class Connect the testbench with your behavior model of MSDAP and test all possible transitions (operation conditions) and reasonable number of inputs/outputs Mark your tested results to show they cover the necessary design corners, and they are correct.

ASIC Design Final project requirement - 4 –Writing requirement A technical report on this project –Objective –Main work –Results –Remarks and comments –Use examples and figures properly –Write in a logical, formal and technical manner Source codes for both behavior model and testbench Simulation (test) results (well marked and explained) A set of power points slides for the presentation of your project in 15 minutes

ASIC Design Final project requirement - 5 –Deadline: Oct. 27, Send electronic copy to TA