October 10, 20001

2 USB 2.0 Peripheral Design Options Dave Podsiadlo Product Marketing Manager Cypress Semiconductor Single-Chip, Internal Microcontroller

October 10, Peripheral Design Options w PHY-PLD/ASIC w Multi-chip: function + external CPU w Single-chip, internal microcontroller w ASIC Integration

October 10, External PHY Multi-Chip: Function + External CPU Single-chip, Internal uController ASIC Design effort MEDIUMMEDIUMLOWHIGH Time to market LONGMEDIUMSHORTLONG NRE costs LOW/HIMEDIUMLOWHIGH Parts cost MEDIUMMEDIUMMEDIUMLOW Pin count HIGHMEDIUMLOWLOW Design Tradeoffs Quick to market Lowest development cost Modest price Quick to market Lowest development cost Modest price

October 10, Single-Chip Issues 1. How fast is it? Can it keep up with the new 480 Mbit/sec rate? Can it get data on and off chip quickly enough? 2. How easy is development? How much of my USB 1.1 experience is usable? 3. How easily does it connect to my system? How much glue logic do I need? Does it introduce any performance bottlenecks? 4. How cost effective is it? What can I replace that’s already in my system?

October 10, How Fast Is It? w An internal microprocessor should not touch 480 Mbit/sec data – Instead, optimize the channel that moves data on and off chip using specialized logic u DMA u Other – Use the CPU for USB housekeeping, I/O, etc. w Fast data transfers require fast control logic – Adaptable to many interfaces u ATA, EPP, etc.

October 10, Speed Example: ATA Hard Drive w Internal data transfer rate is 40 Mbytes/sec. w Avg. sustained transfer rate is 15 Mbytes/sec. w Channel rate is 66.6 Mbytes/sec. – The closer the interface gets to this number, the better it services the drive’s internal buffer u Higher overall performance w USB 2.0 – 13 Bulk packets per microframe max – 13 * 512 * 8 * 1000 = 53,248,000 bytes/sec RPM, 512 Kbyte Internal Buffer

October 10, ATA Hard Drive Data Rates USB Host Buffer Head 40 Disk Drive USB 2.0 Controller USB IF 15 Sustained

October 10, How Easy Is Development? w Continuity with USB 1.1 is the key – Everything you know about 1.1 plus a little extra – (Thank you, USB 2.0 architects) – Differences are real improvements u PING-NYET w Minimize changes – Use the same microprocessor – Hide the protocol enhancements in hardware u Chirp, PING-NYET, DATA2/1/0, etc. – Use the same interface logic – Use the same development tools

October 10, Packet Size Comparison ControlBulkInterruptIsochronous 8, 16, 32, USB 1.1 USB 2.0 Transfer type Packet size

October 10, An Efficient Design Plan w Write ‘1.1’ code using the new endpoint structure w Debug & test using existing tools & OS w Later, run at 2.0 speeds with only slight modification – Configure larger endpoint buffers to take advantage of USB 2.0 high bandwidth

October 10, How Well Does It Connect to My System? w How much ‘glue’ logic is required? w How does it handle two clock domains? – USB & interface logic – May require a FIFO w Data paths – 8 bit – 16 bit w No speed bottlenecks allowed

October 10, How Cost Effective Is It? w Look for a family of parts – ‘Economy’ through ‘Full function’ – Code compatibility up and down the family w Consider the full system cost – The internal microprocessor may replace one already in your system – Interface as peripheral, use internal processor only as a USB housekeeper – USB 2.0 changes the cost equation u Internal processor can be a tiny percentage of the chip area

October 10, Single-Chip Example Low level protocol CRC, PID encode- decode, chirp Deliver WORDS Token Processor EP0, Ping, ACK/NAK/ STALL/ NYET "Chapter 9" Outside Interface High speed logic clock extraction serialize/ deserialize bit stuff NRZI SYNC, EOP 16 Endpoints Endpoint FIFOS & control logic 16 CPU 48 MHz 8051 Program & Data RAM Download Code Data Channel GPIF

October 10, USB Speed: Large Endpoint Buffers And “Zero Time” DMA EP2 EP EP EP6 EP EP EP EP EP EP EP EP8 EP0 IN&OUT EP1 IN EP1 OUT EP8

October 10, Interface Speed: GPIF N1N2N3N4N5 Cycles / branch Data Bus CTL1 OE CTL1 Val 12/321 drive Decision Point? z drivezz 0 WR Strobe data out ready address out RDY WR 20.8 nsec Edge Resolution

October 10, Design Ease: Same Tools

October 10, Value: Three Packages 56 SSOP 8x18x2.3 mm56 mm Price Champ

October 10, Summary: Challenges and Solutions 1. Speed – USB: Large, multiple-buffered endpoints – Interface: fat, dedicated data pipe & fast control logic 2. Development ease – Leverage USB 1.1 experience using same tools 3. System integration – CPU, system glue logic inside 4. Cost effective – Internal microcontroller – Planned family