Virtual Platforms for Memory Controller Design Space Exploration Matthias Jung, Christian Weis, Norbert Wehn University of Kaiserslautern, Germany

Microelectronic Systems Design 64B Standard Memory System msms ss HDD/SSDDRAM L3 shared cache 8-12MB. Memory Controller: 3 Channels L2 private cache 256KB L1 private cache 64KB CORE 16B nsns SRAM Pin limitation due to package Power hungry I/O transceivers Bandwidth RequirementsMemory Wall 512B

Microelectronic Systems Design 3D Stacked Wide I/O DRAM Stacked DRAM dies TSV connections Multiple Channels Increasing bandwidth demand Higher available bandwidth 1 or 2 Channel DDR3 Memory controller bottleneck  New generation of Memory Controllers is required 3D stacked DRAM MPSoC

Microelectronic Systems Design Design Space Exploration with Virtual Platforms Huge design space of 3D-DRAM controller Flexible and cycle approx. models are needed for fast investigation RTL simulation is too slow for system level analysis  TLM based virtual platforms with Synopsys Platform Architect  Speedup of TLM models up to 377x compared to CA 1  Simulating in seconds instead of hours 1 M. Jung, et al. TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, in Proc. HiPEAC Conference 2013, Berlin.

Microelectronic Systems Design Special TLM DRAM Protocol 1 Application specific phases with DECLARE_EXTENDED_PHASE() Phases derived from DRAM commands (Jedec Wide I/O Standard) DRAM commands: ACT, PRE, RD, WR, REFA … Example: 1 M. Jung, et al. TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, HiPEAC, 2013, Berlin.

Microelectronic Systems Design Experiments and Results TLM model was compared with cycle accurate SystemC implementation Tested with Mediabench and CHStone Benchmark traces Speedup up to two magnitudes! 1h 41m 42s

Microelectronic Systems Design Power Modeling of 3D-DRAM with TLM2.0 2 Two parts of power consumption: 1.Background Power 2.Command Power  DRAM Power states accounted with TLM phases 2 M. Jung et al. Power Modelling of 3D-Stacked Memories with TLM2.0, SNUG 2013, Munich ACTWRPREACTRDWRPRE I t

Microelectronic Systems Design Results (Power Simulation) TLM model was compared with a cycle accurate SystemC implementation and the standalone power simulator DRAMPower 3 Tested with Mediabench and CHStone Benchmark traces Deviation max 5% to reference models 3

Microelectronic Systems Design Current Work: Thermal Simulation Co-simulation with 3D- ICE Simulator 3 Traces will be generated from GEM5 4 Closed Loop Control

Microelectronic Systems Design Conclusion 3D stacked DRAMs are the future technology Virtual platform for DSE of new multi-channel Wide I/O DRAM controllers are mandatory DRAM specific TLM protocol was introduced (can be used for any kind of DRAM) Precise Power model presented Early checkpoint for SW implementations Current and Future Work: Advanced scheduling and arbitration algorithms

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