Toshiba Standard Cell Architecture for High Frequency Operation Peter Hsu, Ph.D. Chief Architect Microprocessor Development Toshiba America Electronics Components, Inc. Created 14 March 2001 at the University of Wisconsin in Madison

Layout Architecture for High Frequency Operation2 Disclaimer The ideas, data and conclusions presented here are solely those of the Author, and do not in any way represent Toshiba Corporation policy or strategy.

Layout Architecture for High Frequency Operation3 Introduction High Frequency is Difficult! –Many Issues: Signal Integrity, Power Dissipation,... –My Approach: Disciplined Methodology Global Optimization Outline –Layout –Circuits –Analysis

Layout Architecture for High Frequency Operation4 Layout Strategy Leverage Advanced Technologies –Local Interconnect –Flip-Chip Area Array I/O CAD Tool Compatibility –Parasitic Estimation, Extraction Complex, High Frequency Designs –Robust Power Grid –Flexible Macro Embedding

Layout Architecture for High Frequency Operation5 Metal Usage 300nm 150nm 900nm 450nm 300nm 200nm VSS VDD Signal Via Clock (2x) 600nm450nm Global Wires Short Local Interconnect (M0): Tungsten, Aluminum or Copper Top Metal: Flip-Chip Solder Pads Dimensions are for nominal 0.12µm generation process Contact

Layout Architecture for High Frequency Operation6 Standard Cell Layout Cell Row Power Vias (1 every 6 Tracks) U1.AU1.Z U2.AU2.Z A ZZ U1 VDD U2 VSS A Unrelated Wire Minimum Cell 3 Tracks Crosspoint Power Vias Pins Must Stagger VSS VDD Cell Row Power Vias Minimum Power Rail 6 Tracks From Edge Minimum Pin Width 2 Tracks Local Interconnect Smallest Cell 13 Tracks Double Height Cell

Layout Architecture for High Frequency Operation7 Area Array I/O Decoder Sense Amp. 256 Rows  256 Columns Cell Array 256 Rows  256 Columns Cell Array 307µm 56µm 670µm 538µm 102µm 640µm 225  m pitch 5 I/O Macro (50K  m 2 ) Largest SRAM Macro without sacrificing I/O (16 KBytes) 1.2  m 2.5  m 2 Cell Core VDD Core VSS I/O VDD I/O VSS Signal

Layout Architecture for High Frequency Operation8 Self-Contained –5 Signals –VDDQ, VSSQ –ESD Protection –Latch-Up Ring SoC Flexibility –Many I/O Types –Different Voltages Routing Porosity –50% Channels Free in Global Wiring Layers –Short Output Trace on Top Metal (Electromigration) I/O Macro Cell I/O Macro Use M0+M1+M2 M3 M4 M5 Top Metal M6 Free Routing Channels

Layout Architecture for High Frequency Operation9 SRAM Metal Usage 6-Transistor Cell (1.2  2.1  m ) Bit LinesVSS VDD Word Line #1 Word Line #2 M1 M2 M3 Global Wires (1  or 2  Pitch) SRAM Macro Uses M0+M1+M2 SignalsVDDVSS CAD Tool Inserts M3:M2 Power Vias

Layout Architecture for High Frequency Operation10 Word Line Shielding Signals VDDVSS Cell Array Decoder Sense Amp. Zigzag Minimizes Coupling from M3 Signals to M2 Word Lines when SRAM is Rotated Blocked Tracks M3 Global Wires Bit Lines

Layout Architecture for High Frequency Operation11 Rationale “Effective Area” –Actual Footprint + Routing Disturbance –Larger, More Porous Layout  Faster Bigger Transistors More Space around Bit Lines Shielding SoC –Complex Microarchitecture –Many Small SRAMs

Layout Architecture for High Frequency Operation12 Circuit Design Building Blocks –Latch Array Malleable, Porous, Multi-Port SRAM –Dynamic Wire-OR Gate High Fan-in, Safe, CAD Compatible Power Dissipation –Double Edge Flipflop  50% Clock Tree   30% Peak Chip-Wide –Interpolation Cells

Layout Architecture for High Frequency Operation13 Latch Array G DQ E G DQ E G DQ E G DQ E CK D Q D Q Decoder CK DQ Decoder Read Address Write Address Write Data Read DataTest Mode Latch + Tristate Driver Combinatorial Read Path May Buffer during Place&Route CK DQ DQ Write Pulse Generator Write Enable

Layout Architecture for High Frequency Operation14 Dynamic Wire-OR Gate Input D 1 Input D N G D Q Clock Output Sized for Max. Length Driver Cell Receiver Cell Max. Length by Max-Load, Max-Transition Spec. Limit Max. N by Max-Fanout Spec. Keeper Sized for Max-Fanout Sized for 1 Highest Leverage –Dynamic vs. Static Safe, CAD Compatible –Limit Wire Length using Timing Driven Placement –No Dynamic Inputs _G_G D _Q_Q _G_G D _Q_Q

Layout Architecture for High Frequency Operation15 Double-Edge Flipflop Q D Ck Switching Nodes with Constant “1” Data Low Power –Clock ½ Frequency –Light Clock Load 2 Large + 4 Small Small, Fast § –15P + 15N Transistors Safe, Flexible –Fully Static –Supports Scan ______ § B. Nikolic, et.al., “Sense Amplifier-Based Flip-Flop,” ISSCC 1999.

Layout Architecture for High Frequency Operation16 Interpolation Cells Same Footprint, Shorter Transistors 1X Cell 2X Cell 4X Cell 2 / 3 Power 5 / 6 Power Full Power For Post Route In-Place Optimization

Layout Architecture for High Frequency Operation17 Analysis Signal Integrity –Parasitics “Accurate By Construction” Uniform Metal Density Majority Coupling to Power Rails (Shielding) Speed Yield –Balanced with Resources Area, Power, Design Time –Goal: Adequate Confidence

Layout Architecture for High Frequency Operation18 Uniform Metal Density Algorithmically Generated Filled Metal Uniform Density on all Layers (except Local Interconnect) A ZZ U1 VDD U2 VSS A Post Route Metal Usage

Layout Architecture for High Frequency Operation19 Advantages Design –Accurate Estimation Capacitance has Low Variance –Known Coupling  50% to Adjacent Power Line –Quick Feedback Interconnect-Only Extraction is Accurate Manufacturing –Uniform Etch Resist Loading

Layout Architecture for High Frequency Operation20 Asymmetric Rise-Fall Delays Slow Shrink Slow Elongates DelayDuty Cycle Same Same Size P Transistors Same Size N Transistors

Layout Architecture for High Frequency Operation21 Pros and Cons Advantages –More Compact Cells, Faster Circuits Disadvantages –Need Careful Analysis, Greater Margin Strategy: –Main Library Asymmetric, “No Wasted Space” –Symmetric Subset Gated Clocks, Write Pulse Buffering,...

Layout Architecture for High Frequency Operation22 Speed Yield Management Maximum Process Variation Slow NFast N Fast P Slow P Transistors “Four Corner” Analysis Target Design and Characterize Library Here Process Center Mature Process Variation Setup Time Failures Hold Time Failures Correct Operation Possibly Impossible to Meet Performance Goal, or Needlessly High Effort

Layout Architecture for High Frequency Operation23 Conclusions “Precision Physical Design” –Global Power Grid Macro Routing Porosity –Methodical Signal Integrity Parasitic Extraction Timing Uncertainties (Coupling) –Confident Correctness and Speed