1 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  Digital Design Flow begins with specification of the design at various levels of abstraction.  Design entry phase: Specification of design as a mixture of behavioral Verilog code, instantiation of Verilog modules, and bus and wire assignments

2 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  FPLD Design Flow

3 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  FPLD Design Flow Design Entry Phase

4 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  Presynthesis verification: Generating testbenches for verification of the design and later for verifying the synthesis output

5 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  FPLD Design Flow (Continued) PresynthesisVerification

6 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  Synthesis process: Translating the design into actual hardware of a target device (FPLD, ASIC or custom IC)

7 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  FPLD Design Flow (Continued) Synthesis Process

8 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  Postsynthesis simulation: Testing the behavioral model of the design and its hardware model by using presynthesis test data

9 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  FPLD Design Flow (Continued) PostsynthesisVerification

10 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  Digital Design Flow ends with generating netlist for an application specific integrated circuits (ASIC), layout for a custom IC, or a program for a programmable logic devices (PLD)

11 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  FPLD Design Flow (Continued)

12 Verilog Digital System Design Navabi, 2006 Digital Design Flow HardwareGeneration Design Entry Testbench in Verilog Design Validation Compilation and Synthesis PostsynthesisSimulationTimingAnalysis Digital Design Flow

13 Verilog Digital System Design Z. Navabi, 2006 Verilog HDL  A language that can be understood by:  System Designers  RT Level Designers,  Test Engineers  Simulators  Synthesis Tools  Machines  Has become an IEEE standard

14 Verilog Digital System Design Z. Navabi, 2006 The Verilog Language  The Verilog HDL satisfies all requirements for design and synthesis of digital systems:  Supports hierarchical description of hardware from system to gate or even switch level.  Has strong support at all levels for timing specification and violation detection.  A hardware component is described by the module_declaration language construct in it.

15 Verilog Digital System Design Z. Navabi, 2006 The Verilog Language  The Verilog HDL satisfies all requirements for design and synthesis of digital systems (Continued):  Description of a module specifies a component’s input and output list as well as internal component busses and registers within a module, concurrent assignments, component instantiations, and procedural blocks can be used to describe a hardware component.  Several modules can hierarchically be instantiated to form other hardware structure.  Simulation environments provide graphical front-end programs and waveform editing and display tools.  Synthesis tools are based on a subset of Verilog.

16 Verilog Digital System Design Z. Navabi, 2006 Elements of Verilog  We discuss basic constructs of Verilog language for describing a hardware module.

17 Verilog Digital System Design Z. Navabi, 2006 Elements of Verilog HardwareModules ModuleInstantiations PrimitiveInstantiationsAssignStatements ConditionExpressionProceduralBlocks

18 Verilog Digital System Design Z. Navabi, 2006 Hardware Modules Hardware Modules

19 Verilog Digital System Design Z. Navabi, 2006 Hardware Modules module module-name List of ports; Declarations... Functional specification of module...endmodule  Module Specifications Keyword module module : The Main Component of Verilog Keyword endmodule Variables, wires, and module parameters are declared.

20 Verilog Digital System Design Z. Navabi, 2006 Hardware Modules  There is more than one way to describe a Module in Verilog.  May correspond to descriptions at various levels of abstraction or to various levels of detail of the functionality of a module.  We show a small example and several alternative ways to describe it in Verilog.

21 Verilog Digital System Design Z. Navabi, 2006 Primitive Instantiations Primitive Instantiations

22 Verilog Digital System Design Z. Navabi, 2006 Primitive Instantiations  A Multiplexer Using Basic Logic Gates Logic Gates calledPrimitives

23 Verilog Digital System Design Z. Navabi, 2006 Primitive Instantiations module MultiplexerA (input a, b, s, output w); wire a_sel, b_sel, s_bar; not U1 (s_bar, s); and U2 (a_sel, a, s_bar); and U3 (b_sel, b, s); or U4 (w, a_sel, b_sel); endmodule  Primitive Instantiations Instantiation of Primitives

24 Verilog Digital System Design Z. Navabi, 2006 Assign Statements Assign Statements

25 Verilog Digital System Design Z. Navabi, 2006 Assign Statements module MultiplexerB (input a, b, s, output w); assign w = (a & ~s) | (b & s); endmodule  Assign Statement and Boolean Continuously drives w with the right hand side expression Using Boolean expressions to describe the logic

26 Verilog Digital System Design Z. Navabi, 2006 Condition Expression Condition Expression

27 Verilog Digital System Design Z. Navabi, 2006 Condition Expression module MultiplexerC (input a, b, s, output w); assign w = s ? b : a; endmodule  Assign Statement and Condition Operator Can be used when the operation of a unit is too complex to be described by Boolean expressions Very Effective in describing complex functionalities Useful in describing a behavior in a very compact way

28 Verilog Digital System Design Z. Navabi, 2006 Procedural Blocks Procedural Blocks

29 Verilog Digital System Design Z. Navabi, 2006 Procedural Blocks module MultiplexerD (input a, b, s, output w); reg w; b, s) begin if (s) w = b; else w = a; endendmodule  Procedural Statement alwaysstatement if-elsestatement Can be used when the operation of a unit is too complex to be described by Boolean or conditional expressions Sensitivity list

30 Verilog Digital System Design Z. Navabi, 2006 Module Instantiations Module Instantiations

31 Verilog Digital System Design Z. Navabi, 2006 Module Instantiations module ANDOR (input i1, i2, i3, i4, output y); assign y = (i1 & i2) | (i3 & i4); endmodule// module MultiplexerE (input a, b, s, output w); wire s_bar; not U1 (s_bar, s); ANDOR U2 (a, s_bar, s, b, w); endmodule  Module Instantiation ANDOR module is defined ANDOR module is instantiated

32 Verilog Digital System Design Z. Navabi, 2006 Module Instantiations  Multiplexer Using ANDOR

33 Verilog Digital System Design Z. Navabi, 2006 Component Description in Verilog ComponentDescription DataComponentsControllers

34 Verilog Digital System Design Z. Navabi, 2006 Data Components Data Components

35 Verilog Digital System Design Z. Navabi, 2006DataComponents Interconnection s MultiplexerFlip-Flop CounterFull-Adder Shift-RegisterALU Data Components

36 Verilog Digital System Design Z. Navabi, 2006DataComponents Interconnection s MultiplexerFlip-Flop CounterFull-Adder Shift-RegisterALUMultiplexer Multiplexer

37 Verilog Digital System Design Z. Navabi, 2006 Multiplexer `timescale 1ns/100ps module Mux8 (input sel, input [7:0] data1, data0, output [7:0] bus1); output [7:0] bus1); assign #6 bus1 = sel ? data1 : data0; endmodule  Octal 2-to-1 MUX Selects its 8-bit data0 or data1 input depending on its sel input. Defines a Time Unit of 1 ns and Time Precision of 100 ps. A 6-ns Delay is specified for all values assigned to bus1

38 Verilog Digital System Design Z. Navabi, 2006DataComponents Interconnection s MultiplexerFlip-Flop CounterFull-Adder Shift-RegisterALUFlip-Flop Flip-Flop

39 Verilog Digital System Design Z. Navabi, 2006 Flip-Flop `timescale 1ns/100ps module Flop (reset, din, clk, qout); input reset, din, clk; output qout; reg qout; clk) begin if (reset) qout <= #8 1'b0; else qout <= #8 din; endendmodule  Flip-Flop Description Synchronous reset input A Signal declared as a reg to be capable of holding its values between clock edges An 8-ns Delay A Non-blocking Assignment Flip-Flop triggers on the falling edge of clk Input The Body of always statement is executed at the negative edge of the clk signal

40 Verilog Digital System Design Z. Navabi, 2006DataComponents Interconnection s MultiplexerFlip-Flop CounterFull-Adder Shift-RegisterALUCounter Counter

41 Verilog Digital System Design Z. Navabi, 2006 Counter `timescale 1ns/100ps module Counter4 (input reset, clk, output [3:0] count); output [3:0] count); reg [3:0] count; clk) begin clk) begin if (reset) count <= #3 4'b00_00; if (reset) count <= #3 4'b00_00; else count <= #5 count + 1; else count <= #5 count + 1; end endendmodule  Counter Verilog Code A 4-bit modulo-16 Counter Constant Definition 4-bit Register When count reaches 1111, the next count taken is 10000

42 Verilog Digital System Design Z. Navabi, 2006DataComponents Interconnection s MultiplexerFlip-Flop CounterFull-Adder Shift-RegisterALUFull-Adder Full-Adder

43 Verilog Digital System Design Z. Navabi, 2006 Full-Adder `timescale 1ns/100ps module fulladder (input a, b, cin, output sum, cout); assign #5 sum = a ^ b ^ cin; assign #3 cout = (a & b)|(a & cin)|(b & cin); endmodule  Full-Adder Verilog Code A combinational circuit All Changes Occur after 5 ns All Changes Occur after 3 ns One delay for every output: tPLH and tPHL

44 Verilog Digital System Design Z. Navabi, 2006DataComponents Interconnection s MultiplexerFlip-Flop CounterFull-Adder Shift-RegisterALUShift-Register Shift-Register

45 Verilog Digital System Design Z. Navabi, 2006 Shift-Register `timescale 1ns/100ps module ShiftRegister8 (input sl, sr, clk, input [7:0] ParIn, input [1:0] m, output reg [7:0] ParOut); input [1:0] m, output reg [7:0] ParOut); clk) begin case (m) case (m) 0: ParOut <= ParOut; 0: ParOut <= ParOut; 1: ParOut <= {sl, ParOut [7:1]}; 1: ParOut <= {sl, ParOut [7:1]}; 2: ParOut <= {ParOut [6:0], sr}; 2: ParOut <= {ParOut [6:0], sr}; 3: ParOut <= ParIn; 3: ParOut <= ParIn; default: ParOut <= 8'bX; default: ParOut <= 8'bX; endcase endcaseendendmodule An 8-bit Universal Shift Register 2 Mode inputs m[1:0] form a 2-bit number m=0 : Does Nothing m=3 : Loads its Parallel input into the register m=1,2: Shifts Right and Left Case Statement With 4 case-alternatives and default Value

46 Verilog Digital System Design Z. Navabi, 2006 Shift-Register (Continued) `timescale 1ns/100ps module ShiftRegister8 (input sl, sr, clk, input [7:0] ParIn, input [1:0] m, output reg [7:0] ParOut); input [1:0] m, output reg [7:0] ParOut); clk) begin case (m) case (m) 0: ParOut <= ParOut; 0: ParOut <= ParOut; 1: ParOut <= {sl, ParOut [7:1]}; 1: ParOut <= {sl, ParOut [7:1]}; 2: ParOut <= {ParOut [6:0], sr}; 2: ParOut <= {ParOut [6:0], sr}; 3: ParOut <= ParIn; 3: ParOut <= ParIn; default: ParOut <= 8'bX; default: ParOut <= 8'bX; endcase endcaseendendmodule Shift Right: The SL input is concatenated to the left of ParOut Shifting the ParOut to the left

47 Verilog Digital System Design Z. Navabi, 2006DataComponents Interconnection s MultiplexerFlip-Flop CounterFull-Adder Shift-RegisterALUALU ALU

48 Verilog Digital System Design Z. Navabi, 2006 ALU `timescale 1ns/100ps module ALU8 (input [7:0] left, right, input [1:0] mode, input [1:0] mode, output reg [7:0] ALUout); output reg [7:0] ALUout); right, mode) begin right, mode) begin case (mode) case (mode) 0: ALUout = left + right; 0: ALUout = left + right; 1: ALUout = left - right; 1: ALUout = left - right; 2: ALUout = left & right; 2: ALUout = left & right; 3: ALUout = left | right; 3: ALUout = left | right; default: ALUout = 8'bX; default: ALUout = 8'bX; endcase endcaseendendmodule  An 8-bit ALU 2-bit mode Input to select one of its 4 functions AddSubtractANDOR

49 Verilog Digital System Design Z. Navabi, 2006 ALU (Continued) `timescale 1ns/100ps module ALU8 (input [7:0] left, right, input [1:0] mode, input [1:0] mode, output reg [7:0] ALUout); output reg [7:0] ALUout); right, mode) begin right, mode) begin case (mode) case (mode) 0: ALUout = left + right; 0: ALUout = left + right; 1: ALUout = left - right; 1: ALUout = left - right; 2: ALUout = left & right; 2: ALUout = left & right; 3: ALUout = left | right; 3: ALUout = left | right; default: ALUout = 8'bX; default: ALUout = 8'bX; endcase endcaseendendmodule  An 8-bit ALU The Declaration of ALUout both as output and reg: Because of assigning it within a Procedural Block Blocking Assignments default alternative puts all Xs on ALUOut if mode contains anything but 1s and 0s

50 Verilog Digital System Design Z. Navabi, 2006DataComponents Interconnection s MultiplexerFlip-Flop CounterFull-Adder Shift-RegisterALUInterconnections

51 Verilog Digital System Design Z. Navabi, 2006 Interconnections  Partial Hardware Using MUX8 and ALU Mux8 and ALU examples forming a Partial Hardware

52 Verilog Digital System Design Z. Navabi, 2006 Interconnections ALU8 U1 (.left(Inbus),.right(ABinput),.mode(function),.ALUout(Outbus) );.mode(function),.ALUout(Outbus) ); Mux8 U2 (.sel(select_source),.data1(Aside),.data0(Bside),.bus1 (ABinput));  Verilog Code of The Partial Hardware Example Instantiation of ALU8 and MUX8 u1 and u2 : Instance Names A Set of parenthesis enclose port connections to the instantiated modules

53 Verilog Digital System Design Z. Navabi, 2006 Interconnections ALU8 U1 ( Inbus, ABinput, function, Outbus ); Mux8 U2 ( select_source, Aside, Bside, ABinput );  Ordered Port Connection An Alternative format of port connection The actual ports of the instantiated components are excluded The list of local signals in the same order as their connecting ports

54 Verilog Digital System Design Z. Navabi, 2006 ControllersComponentDescription DataComponentsControllers Controllers

55 Verilog Digital System Design Z. Navabi, 2006 Controllers  Controller Outline

56 Verilog Digital System Design Z. Navabi, 2006 Controllers  Controller:  Is wired into data part to control its flow of data.  The inputs to it controller determine its next states and outputs.  Monitors its inputs and makes decisions as to when and what output signals to assert.  Keeps the history of circuit data by switching to appropriate states.  Two examples to illustrate the features of Verilog for describing state machines:  Synchronizer  Sequence Detector

57 Verilog Digital System Design Z. Navabi, 2006 ControllersControllers SynchronizerSequenceDetector

58 Verilog Digital System Design Z. Navabi, 2006 SynchronizerControllers SynthesizerSequenceDetector Synchronizer

59 Verilog Digital System Design Z. Navabi, 2006 Synchronizer  Synchronizing adata

60 Verilog Digital System Design Z. Navabi, 2006 Synchronizer `timescale 1ns/100ps module Synchronizer (input clk, adata, output reg synched); output reg synched); clk) if (adata == 0) synched <= 0; else synched <= 1; endmodule  A Simple Synchronization Circuit If a 1 is Detected on adata on the rising edge of clock, synched becomes 1 and remains 1 for at least one clock period

61 Verilog Digital System Design Z. Navabi, 2006 Sequence Detector Controllers SynthesizerSequenceDetector Sequence Detector

62 Verilog Digital System Design Z. Navabi, 2006 Sequence Detector  State Machine Description Searches on it’s a input for the 110 Sequence When the sequence is detected, the w Output becomes 1 and stays 1 for a complete clock cycle

63 Verilog Digital System Design Z. Navabi, 2006 Sequence Detector  Sequence Detector State Machine Initia l State States are named: s0, s1, s2, s3 The State in which the 110 sequence is detected. It Takes at least 3 clock periods to get to the s3 state A Moore Machine Sequence Detector

64 Verilog Digital System Design Z. Navabi, 2006 Sequence Detector module Detector110 (input a, clk, reset, output w); parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11; reg [1:0] current; clk) begin if (reset) current = s0; if (reset) current = s0; else else case (current) case (current) s0: if (a) current <= s1; else current <= s0; s0: if (a) current <= s1; else current <= s0; s1: if (a) current <= s2; else current <= s0; s1: if (a) current <= s2; else current <= s0; s2: if (a) current <= s2; else current <= s3; s2: if (a) current <= s2; else current <= s3; s3: if (a) current <= s1; else current <= s0; s3: if (a) current <= s1; else current <= s0; endcase endcaseend assign w = (current == s3) ? 1 : 0; endmodule  Verilog Code for 110 Detector

65 Verilog Digital System Design Z. Navabi, 2006 Sequence Detector module Detector110 (input a, clk, reset, output w); parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11; reg [1:0] current; clk) begin if (reset) current = s0; if (reset) current = s0; else else  Verilog Code for 110 Detector Behavioral Description of the State Machine Parameter declaration defines constants s0, s1, s2, s3 A 2-bit Register

66 Verilog Digital System Design Z. Navabi, 2006 Sequence Detector clk) begin if (reset) current = s0; if (reset) current = s0; else else case (current) case (current) s0: if (a) current <= s1; else current <= s0; s0: if (a) current <= s1; else current <= s0; s1: if (a) current <= s2; else current <= s0; s1: if (a) current <= s2; else current <= s0; s2: if (a) current <= s2; else current <= s3; s2: if (a) current <= s2; else current <= s3; s3: if (a) current <= s1; else current <= s0; s3: if (a) current <= s1; else current <= s0; endcase endcaseend  Verilog Code for 110 Detector if-else statement checks for reset At the Absence of a 1 on reset The 4 Case-alternatives each correspond to a state of state machine

67 Verilog Digital System Design Z. Navabi, 2006 Sequence Detector  State Transitions on Corresponding Verilog Code

68 Verilog Digital System Design Z. Navabi, 2006 Sequence Detector end assign w = (current == s3) ? 1 : 0; endmodule  Verilog Code for 110 Detector Assigns a 1 to w output when Machine Reaches to s3 State Outside of the always Block: A combinational circuit