Microcomputer Systems Project By Shriram Kunchanapalli

ADSP Blackfin BF533 ADSP-BF533 Emdedded Processor Data Sheet ( Revision E )Notes on Blackfin Processor [PDF] : Belongs to the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture( MSA ). Highly integrated system-on-a-chip solutions for the next generation of digital communication and consumer multimedia applications. By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a UART port, an SPI port, two serial ports (SPORTs), four general-purpose timers (three with PWM capability), a real-time clock, a watchdog timer, and a parallel peripheral interface.

Configuration of PPI - DMA Engine PPI must be used with the processor's DMA engine. PPI DMA channel must be configured for either transmit or receive operation First - Configure PPI's DMA channel to use PPI interface DMA Engine generates interrupts upon completion of a row, frame, or partial-frame transfer DMA Engine coordinates the origination or destination point for the data that is transferred through the PPI Reference: Page 31/34 of PPI of the Hard. Ref. manual

ITU-R 656(formerly known as CCIR-656) reference: page13-14/34 (525/60)NTSC and (625/50) PAL systems Processor supports only the Bit-parallel mode of ITU-R 656 mode - 8- and 10- bit video element widths are supported. In this mode, the Horizontal(H), Vertical(V), and Field(F) signals are sent as embedded part of video datastream in series of bytes that form a control word SAV occurs on 1-0 transition of H EAV occurs on 0-1 transition of H

NTSC Operations Reference:PPI Document - Page 16/34 Entire Video field = Active Video+Horizontal Blanking( the space between EAV and SAV) and Vertical Blanking(V=1) - Horizontal Blanking - The interval between the start of active video and the end of active video - In many applications, video streams like CIF, QCIF other than NTSC/PAL formats can be employed Processor interface is flexible enough to accomodate different row and field lengths. a CIF image could be formatted to be "656-compliant" - proper EAV/SAV codes and EAV,SAV values define the range of the image for each line, and the V,F codes can be used to delimit fields and frames

Game Design Board Design and Game Logic Representation of Images in Memory Drawing Shapes University of Calgary Library Classes NTSC Standard

Game Implementation Main header file o Functions  Check For Win  Drawing Shapes – Lines, Dots o Software Reusability OOP concept o Global Attributes Improvements o Header Files o Local Attributes o Working around Duplication of Code

Conclusion Video Utility class takes care of conversion of a 486x720 to an image of ITU_656 format and setting to default color of gray Improvements: o User Interactive o Computer Player – application of AI o 3D version of the Game

References Dr.Kepuska’s Slides o Image and Video Processing(HSV),Audio Processing Solution, Lab3 - Audio Interface, o Resources and Links powerpoint Video Output, Utility Library The Scientist and Engineer’s Guide to Digital Signal Processing Ch 1, 4, 14, 15, [22], [23]