DRRA Dynamically Reconfigurable Resource Array Ahmed Hemani Dept. Of ES, School of ICT, KTH Kista Email: hemani@kth.se Website: www.it.kth.se/~hemani

Dynamically Reconfigurable Resource Array DRRA Dynamically Reconfigurable Resource Array ASIC like arbitrary parallelism, local and hierarchical control Software like flexibility Regular, seamless topology Easy mapping Perfect energy and performance prediction Full custom will compensate the reconfiguration overheads Private execution environments Minimal movement of data Move Logic Not Data Vectorising, Symbolic Assembler under development C/Matlab compiler to be developed

3. DRRA System Architecture DRRA System Concept + Reconfigurable Arithmetic Resource Pool . . . Reconfigurable Control Logic Resource Pool Register File Pool Protocol Processor Pool 3D Distributed Memory Pool Application Processor - RISC Run Time Management System Processor -RISC External Data Exchange Interconnect Control and Configuration Interconnect External IF Manager Resource Application Runtime Management System Power Management Application Controller (SW) Protocol Processing Layers Controller (SW+CW) Algorithm Datapath Physical Layer Controllers (HW) Modem/Codec etc. Controller Tx/Encode etc. Ctrlr Rx/Decode etc. Ctrlr Applications run concurrently in their private execution environments in DRRA Application 1 Application 2 Application 3 Private execution environments for three applications look at http://web.it.kth.se/~hemani/DRRA%20Summary.pdf 3. DRRA System Architecture

DRRA PHY Layer Fabric 12 16b buses 7 X 2 16b buses Regiser File 16b X 64 2 Read , 2 Write Ports Burst Mode, Shift and Circular Buffer Mode Addrs Gen. Unit Context Memory Morphable DPU 16 bit, 32 bit accumulator 4 Inputs, 2 Outputs MAC, Butterfly, 5 stage pipeline ADD/SUB tree Sum of Difference, Difference of Sum LFSR, Counter, Comparators Windowed Truncation, Saturation Context Memory Sequencer Simple sequential flow Conditional and Counter based Loop and branching Controls Register File, mDPU and Interconnect switches Interconnect 3 hop, Sliding window Fully connected Segmented 7 hop Wires Circuit Switchd Network Local Config Memory Fabric Scalabe, Regular Topology Interfaces to Distributed Memory and Central Controller

Initial Results Layout of 7X2 mDPUs, Regfiles and Sequencers, Corresponding to the fabric shown on the previous slide 90 nm, 720 MHz 64 point FFT – radix -2 DIT ~50 nJ, ~300 ns. Unoptimised N.B. 4 mDPUs and 4 Regfiles used 90 nm, 720 MHz 11 tap FIR– Symmetric ~300 pJ, ~6 ns. Unoptimised N.B. 1 mDPU and 1 Regfile used Long term goal is to come very close to ASIC with full custom datapath

Vectorising Symbolic Assembler N is the order of the filter. M is the degree of parallelism All serial parallel solutions are concisely captured by this pattern

The mapping for N=101, M = 7 x0 x6 x100 x94 x7 x13 x93 x87 x14 x20 x86 + × C7-C13 C0-C6 C14-C20 C21-C27 C28-C34 C35-C42 C43-C50 refi_0_0 refi_0_1 refi_0_2 refi_0_3 refi_0_4 refi_0_5 refi_0_6 refi_1_0 refi_1_1 refi_1_2 refi_1_3 refi_1_4 refi_1_5 refi_1_6 p0 p1 p2 p3 p4 p5 p6 adderTree4 newSample convSum

Protocol Processor Concept API To Higher Layer Constants Registers Frag / Defrag Error Chk Encryp/ Decryp Memory Bit Field Analysis Control and Timing API To Lower Layer For explaination look at http://web.it.kth.se/~hemani/DRRA%20Summary.pdf Go to section 5: Protocol Processor Architecture

REXAPP Radio Experimentation & Prototyping Platform Baseband Rx Protocol Processing Layers Application Layer Baseband Tx RF/Analog Tx RF/Analog Rx Configurable Chanel Model Control, Configuration, Debug and Monitoring Control, Configuration, Debug and Monitoring Resources Host Interface Configurable RF/Analog Impairment Models High Capacity, High Bandwidth Storage

Vision for the future Don’t stop dreaming ! RF/Analog/Sensors/peripherals Logic Tile - Giga Gates Volatile Memory - GigaBytes Non-Volatile Memory - TeraBytes Don’t stop dreaming !