Low Power Wireless Design Dr. Ahmad Bahai National Semiconductor

New paradigm in Wireless Bits/s/HzJ/Bits/s/Hz Design for worst case Configurable Design Power Efficiency Configurability CentralizedHybrid Architecture

Power efficiency Cellular WLAN UWB Distance to IP Network Miles Yards Feet Pervasive IP TX Power 100 mW 10 mW mW Tx power ~ Circuit power (1nJ/bit transmission energy- 10 m distance) Power = Tx power + Circuit power Data Rate 100s kbps 10s mbps 100s mbps

Comm Theory, Asym Values Absolute minimum energy for reliable transmission of 1 bit of information Min switching energy for digital gate (1 1.6X10

Transmission vs. Circuit Energy Communication Theory usually considers Transmission energy only! Transmission Energy Spectral Efficiency But Optimal Bandwidth-time pair? Optimal Bandwidth-time pair?

Total Energy (MQAM)

Platform MAC layer including ARM and PCI PCI interface Phy Tx/RX RF/Analog supporting up to 4 radios

Power profile in WLAN (TX)

Power profile in WLAN (RX)

Channel Effect IMEC Collaboration

Comm Theory Approach Bandwidth Power Mask Interference Data rate BER Channel Modulation Coding Synchronization SiNR Dynamic Range Margin Noise figure EnergyQoS Statistical performance MAC State machines Adaptive design

Energy and Throughput Common Approach: Define SINR and capacity as Assume BPSK with BER target of 10e-q, bandwidth W and target data rate of R>C; then we can show that minimal power vector supporting network topology for low SIR can be derived as:

Design Strategy System level approach to low power communication design Case study: ZigBee Profile the power consumption Study effect of multi-layer optimization A new design strategy

IEEE PHY Direct Sequence Spread Spectrum (DSSS) radio 2Mchip/s OQPSK modulation 1 symbol = 32-chip PN sequence 1 symbol = 4 bits PHY data rate: 250kbps Transmit power up to 0 dBm BAND COVERAGE DATA RATE CHANNEL(S) 2.4 GHzISM Worldwide 250 kbps MHzEurope 20 kbps MHzISM Americas 40 kbps 10

spec. summary Symbol rate and Tx RF accuracy: +/- 40 ppm Packet Error Rate (PER)  Defined for PSDU of 20x8 bits Sensitivity: -85 dBm (PER < 1%) RSSI: sens. level +10 dB, 40 dB range (+/- 6dB) Max input level: -20 dBm Jamming resistance (interference performance)  0 dB for adjacent channels (ref: -82 dBm)  30 dB for alternate channels (ref: -82 dBm)  Interferer is compliant interferer Tx Error Vector Magnitude : < 35% for 1000 chips Tx PSD: -20 dB or –30 dBm |f-Fc| > 3.5 MHz (rbw 100kHz) Output power: > -3 dBm max power setting) Rx-Tx turnaround time: 12 Symbols (192 ms)

ZBIC, one-chip solution ZBIC

4-state/Transition Energy Profile Shutdown 80 nA Idle 396 uA RX 19.6 mA TX -25 dBm: 8.42 mA -15 dBm: 9.71 mA -10 dBm: 10.9 mA -7 dBm: mA -5 dBm: mA -3 dBm: mA -1 dBm: mA 0 dBm: mA VDD = 1.8V 970 us 691pJ 194 us 6.63 uJ 194 us 6.63 uJ Transition Energy  T(transition) x I(target state) x VDD IMEC/MIT Power Profile

Observations Efficiency (energy/bit) changes with: Larger packet size Transmit power control Network Load Link layer performance Contention Channel Coding

Power Breakdown Breakdown between the states In high load, the node spends more time in RX than in TX mode! IMEC/MIT

More comprehensive Energy model Energy efficiency metric: New model for total energy was used to optimize back off strategy in an ad-hoc network. TX, RX, Collision, sensing, Transitions, ramp up

Energy Efficient Backoff Proposed backoff Standard backoff Resetting back-off is more energy efficient than DCF backoff due to carrier sensing overhead.

Summary Statistical Performance Analysis: New design paradigm in communication Mixed signal processing and cross layer optimization Configurable and low power design: Key Design objectives Multimode/Multi-layer Optimization Analog/mixed signal: critical in power consumption