ICE-DIP project Parallel processing on Many-Core processors ICE-DIP introduction at Intel › 22/7/2014

Agenda 22/07/2014 Przemysław Karpiński – ICE-DIP Project 2  CERN experiments and Online processing  High Level Trigger (HLT) architecture  The ICE-DIP Project  The research focus

Physics Experiments at CERN 22/07/2014 Przemysław Karpiński – ICE-DIP Project 3

Particle Detector 22/07/2014 Przemysław Karpiński – ICE-DIP Project 4

Online processing system 22/07/2014 Przemysław Karpiński – ICE-DIP Project 5

Trigger Data Acquisition(TDAQ) system – ATLAS, before upgrade 22/07/2014 Przemysław Karpiński – ICE-DIP Project 6

Trigger Data Acquisition(TDAQ) system – ATLAS, after upgrade 22/07/2014 Przemysław Karpiński – ICE-DIP Project 7

22/07/2014 Przemysław Karpiński – ICE-DIP Project 8

Science and Technology PoW reference ThemeResearcherWPESRChallengeResearch Silicon Photonics Marcel Zeiler WP1ESR1Need affordable, high throughput, radiation tolerant links Design, manufacture, test under stress a Si- photonics link Reconfi- gurable Logic Srikanth Sridharan WP2ESR2Reconfigurable logic is used where potentially more programmable CPUs could be proposed A hybrid CPU/FPGA data pre- processing system DAQ networks Grzegorz Jereczek WP3ESR3Bursts in traffic are not handled well by off-the-shelf networking equipment Loss-less throughput up to multiple Tbit/s with new protocols High performanc e data filtering Aram Santogidis Przemysław Karpiński WP4ESR4Accelerators need network data, but have very limited networking capabilities Direct data access for accelerators (network- bus-devices-memory) ESR5Benefits of new computing architectures are rarely fully exploited by software Find and exploit parallelization opportunities and ensure forward scaling in DAQ networks Material from Andrzej Nowak - ICE-DIP overview

7 Degrees Of Freedom 22/07/2014 Przemysław Karpiński – ICE-DIP Project 10 Picture from: A. Nowak – „The evolving marriage of hardware and software”

7 Degrees Of Freedom Prison 22/07/2014 Przemysław Karpiński – ICE-DIP Project 11 Picture from: A. Nowak – „The evolving marriage of hardware and software”

7 Degrees Of Freedom Prison 22/07/2014 Przemysław Karpiński – ICE-DIP Project 12 Picture from: A. Nowak – „The evolving marriage of hardware and software” Increase clock, increase speed. Can we do that?

7 Degrees Of Freedom Prison 22/07/2014 Przemysław Karpiński – ICE-DIP Project 13 Picture from: A. Nowak – „The evolving marriage of hardware and software” Increase clock, increase speed. Can we do that? Do we have vectors ready for computation?

7 Degrees Of Freedom Prison 22/07/2014 Przemysław Karpiński – ICE-DIP Project 14 Picture from: A. Nowak – „The evolving marriage of hardware and software” Increase clock, increase speed. Can we do that? Do we have vectors ready for computation? Can we predict operation dependencies?

7 Degrees Of Freedom Prison 22/07/2014 Przemysław Karpiński – ICE-DIP Project 15 Picture from: A. Nowak – „The evolving marriage of hardware and software” Increase clock, increase speed. Can we do that? Do we have vectors ready for computation? Can we predict operation dependencies? Are ports equally capable?

7 Degrees Of Freedom Prison 22/07/2014 Przemysław Karpiński – ICE-DIP Project 16 Picture from: A. Nowak – „The evolving marriage of hardware and software” Increase clock, increase speed. Can we do that? Do we have vectors ready for computation? Can we predict operation dependencies? Are ports equally capable? Are threads competing for resources?

7 Degrees Of Freedom Prison 22/07/2014 Przemysław Karpiński – ICE-DIP Project 17 Picture from: A. Nowak – „The evolving marriage of hardware and software” Increase clock, increase speed. Can we do that? Do we have vectors ready for computation? Can we predict operation dependencies? Are ports equally capable? Are threads competing for resources? Are the cores competing for resources?

7 Degrees Of Freedom Prison 22/07/2014 Przemysław Karpiński – ICE-DIP Project 18 Picture from: A. Nowak – „The evolving marriage of hardware and software” Increase clock, increase speed. Can we do that? Do we have vectors ready for computation? Can we predict operation dependencies? Are ports equally capable? Are threads competing for resources? Are the cores competing for resources? Are the sockets communicating with each other?

CERN software › Multiple „big” frameworks › Code developed by physicists › Code developed in a hurry › Detector systems specific knowledge › Development criteria change over time 22/07/2014 Przemysław Karpiński – ICE-DIP Project 19

CERN software › Multiple „big” frameworks - > C++ code lines › Code developed by physicists - unexperienced in computer science › Code developed in a hurry - people employeed for short term contracts › Detector systems specific knowledge - custom hardware › Development criteria change over time - physics change 22/07/2014 Przemysław Karpiński – ICE-DIP Project 20

Many-core processors in high throughput data filtering applications 22/07/2014 Przemysław Karpiński – ICE-DIP Project 21 Will conduct research on the Intel Xeon Phi: Time and energy costs in the context of High Energy Physics Programmability in terms of existing frameworks Deployment model and scalability Performance tuning methodology

Current Ideas › Implicit vectorization library ( › Template metaprogramming for high hardware utilisation › LHCb Framework abstraction Layer for MIC ( › Performance Auto-tuning 22/07/2014 Przemysław Karpiński – ICE-DIP Project 22

Questions and Answers 22/07/2014 Przemysław Karpiński – ICE-DIP Project 23