Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 3 Eike Schweißguth Institute MD, University of Rostock

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Recap Slide 2 RC Adder Register RC Adder Register Partial Products Previous Coefficient Register

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Multiplier with Carry Save Adders CS Adder Register CS Adder Partial Products Previous Coefficient Register CS Adder Register Pipelined RC Adder Register

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Adder RC Adder with 4 pipeline stages only one adder  adder architecture does not affect metric a lot minor improvement possible by using more efficient adder architecture

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Coefficients & Pipelining total number of pipeline stages: 6 coefficients optimized to keep the filter response as close as possible to the reference design while producing a maximum of 3 partial products reduced overall adder width because the last 16 bits are cut off at the output anyway

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Tool Optimization – Frequency max_dynamic_power  negative effect max_leakage_power  negative effect frequency:  tool automatically optimizes the design to meet the clock constraint  e.g. testing of different logic implementations, transistor upsizing, logic splitting

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Tool Optimization – Frequency far away from the limits of the logic implementation: dynamic power increases nearly linearily with the frequency, leakage power is nearly constant leakage power and dynamic power increase significantly when reaching the limits of the design  “sweet spot” has to be found f [GHz] Metric [GHz/(mW*µW)]

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Tool Optimization – Library Selection LVT Library: HVT Library: SVT Library:  useful for achieving high frequencies  more than 2 GHz possible with the current design  bad metric due to power consumption (high leakage power)  significantly lower leakage power  still high frequency possible  best metric  tradeoff between leakage power and frequency

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 9 Metric Frequency f [MHz]1199 # of Pipeline Stages6 Area [µm²] Metric [GHz/(mW*µW)]0.790 Dynamic Power [mW] Leakage Power [nW] Total Power [mW]

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 10 Frequency Response

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 11 Thank you for your attention!