© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Introduction Purpose:  This training module provides a technical description of Renesas MCU’s, Processing Power, Clocks, and Power Management functions. Objectives:  Describe the basic core/register model and instruction format for the M16C core  Describe the hardware features and advanced program instructions that minimize code size and maximize execution speed  Compare processing power of the M16C to RISC type instruction sets  Describe the core and peripheral clock circuits of the M16C  List the low power modes of operation for the M16C and the currents required to operate in those modes  Describe the Key Interrupt feature which is uniquely suited for restoring the MCU from low power modes Content:  21 Pages  4 Questions Learning Time:  30 minutes

© 2008, Renesas Technology America, Inc., All Rights Reserved M16C/60 CPU Core/Register Model R0HR0L R1HR1L R2 R3 A0 A1 FB 08 / / / / R0HR0L R1HR1L R2 R3 A0 A1 FB 08 / / / / bits 16 bits SB 016 ISP USP FLG PC INTB Register Banks 2 x 32-bit Register ( R0 / R1, R2 / R3 ) or 4 x 16-bit Register ( R0, R1, R2, R3 ) or 4 x 8-bit registers ( R0L, R0H, R1L, R1H ) 2 x 16-bit Address / General-Purpose Register A0, A1 1 x 32-bit Address Register [ A0, A1 ] SB and FB registers can be used in indexed addressing modes ( e.g. C-language stack frame addressing ) 2 stack pointers allow exclusive H/W interrupt stack and OS stack Flag Register 20-bit Program Counter Interrupt Table Pointer allows multiple Interrupt Vector Tables 20 bits

© 2008, Renesas Technology America, Inc., All Rights Reserved 3 Format of Instructions Example: MOV.W:GR0, R1 MOV.size/.length:formatsrc, dest Mnemonic Size specifier Jump distance specifier Format specifier OperationOperand Note: order is opposite from most assemblers R0 R1 08 / /

© 2008, Renesas Technology America, Inc., All Rights Reserved Distribution of Instruction Execution Cycles M16C/60 0.0% 10.0% 20.0% 30.0% 40.0% 50.0% 60.0% 0.0% 10.0% 20.0% 30.0% 40.0% 60.0% 1cycle 2cycle3cycle4cycle 5cycle 6cycle 7cycle 8cycle 9cycle 10cycle 11cycle more 2.1% 18.0% 50.8% 11.3% 3.3% 3.0% 4.2% 2.4% 3.2% 0.2% 1.4% Combination of instructions and addressing modes % More than 70% of Instructions Take 3 Cycles or less

© 2008, Renesas Technology America, Inc., All Rights Reserved High Speed Operations Execution cycle of multiplication Signed multiplication Unsigned multiplication M16C/60 conventional MCU MCU A (16-bit) MCU B (16-bit) Cycle 20

© 2008, Renesas Technology America, Inc., All Rights Reserved Memory-Memory Operation (M16C/62) Register-register, register-memory, and memory-memory operations are available Accumulator or Load and Store Architecture Register-memory operation ROM efficiency of memory-memory operation 4-byte 6-byte RAM1 RAM2 Acc + RAM1 RAM2 + LDA A, RAM1 AND A, RAM2 STA A, RAM2 AND.B RAM1[SB], RAM2[SB]

© 2008, Renesas Technology America, Inc., All Rights Reserved 7 Bit Clear, Bit Set Instruction Operation BSET 42,RAM BCLR BCLR dest MnemonicDescription format BSET dest BSET b0b7 RAM RAM+1 RAM+5 Example BCLR 3,RAM BCLR 1,R0 BCLR [A0] Set this bit Bits can be addressed within a byte or directly from an offset in a 64k bit (8k byte) range BSET 2,RAM+5 Or

© 2008, Renesas Technology America, Inc., All Rights Reserved 8 Calculate Sum-of-Products, DSP Type Instruction RMPA RMPA.size Mnemonic Description format Multiplicand address : A0 Multiplier address : A1 Loop counter : R3 Sum-of products register (result of operation) : R2R0 (.W is specified) / R0 (.B is specified) If an overflow occurs during operation, the O flag is set to terminate the operation. If an interrupt request is received during instruction execution, the interrupt is acknowledged after the sum-of product addition is completed. Example RMPA.W x A1 R0R2 Result of Operation R3 The multiplier multiplies the contents of A0 and A1 Multiplier At address A1 A0 Multiplicand At address A0 A0 A1 4 ALU adds the result of A0 x A1 to the current value of R2R0 and stores it back into R2R0 Multiplier Result + R0R2 ALU Current Value of R2R0 Loop Counter Loop counter is decremented If R3=0 operation complete

© 2008, Renesas Technology America, Inc., All Rights Reserved 11 Clock Circuit BCLK is the CPU clock CPU can select from multiple inputs for its operating frequency. Sub Clock Main Clock 1/2

© 2008, Renesas Technology America, Inc., All Rights Reserved 12 CPU Clock Sources BCLK Clock Speeds (CPU Clock)  f(Xin) divided by 1,2,4,8 or 16  f(Xcin) Default BCLK is f(Xin) divided by 8 Change clocks using System Clock Control Registers System Clock Control Registers are protected from accidental writes by Protect Register The M16C/62P also has a PLL circuit which allows 24MHz operation with a 12MHz Crystal 1/2

© 2008, Renesas Technology America, Inc., All Rights Reserved 13 Peripheral Clock Sources Each peripheral block can select clock ratio Serial I/O blocks  f1, f8, f32 Timers  f1, f8, f32, fc32 Analog to Digital Converter  fAD = f(Xin)  fAD can be divided by 1,2 or 4 to clock the ADC  The ADC should not be clocked >10 Mhz Formula Key: f1 = f(Xin)/1 f8 = f(Xin)/8 f32 = f(Xin)/32 fc32 = f(XCin)/32

© 2008, Renesas Technology America, Inc., All Rights Reserved 14 Low Power Operation - Wait Mode Executing a WAIT Instruction stops BCLK Peripheral Clocks will continue to run unless configured to stop by control bit in System Clock Register ( Peripherals supplied by fc32 will still receive clock) An interrupt is used to exit Wait mode For M16C/62A Icc in Wait Mode :  4 uA typical with f(Xcin)= 32kHz and running one timer using fc32

© 2008, Renesas Technology America, Inc., All Rights Reserved 15 Low Power Operation - Stop Mode Executing a STOP Instruction stops oscillators Peripherals are disabled since there are no clocks except:  Timers can be used to count external pulses  UARTs and SIOs can be used with external clocks An Interrupt is used to exit Stop mode For M16C/62A Icc in Stop Mode :  1 uA 25°C  20 uA 85°C

© 2008, Renesas Technology America, Inc., All Rights Reserved 16 Wait/RTC Initialize XC (Sub-clock) Set 1 second timer from XC Mode=Run Perform Process Functions Enter WAIT Mode WAIT Waits for Timer ISR or Wake ISR Clock Mode=Unchanged Update Clock Counter Return One Second Timer ISR Clock Mode=Run Return Wake ISR Yes No Yes ISR can occur at any point in the process When complete it will return to the next step in the process Mode=Wait

© 2008, Renesas Technology America, Inc., All Rights Reserved 17 Key Input Interrupt P10 7 /KI 3 P10 6 /KI 2 P10 5 /KI 1 P10 4 /KI 0

© 2008, Renesas Technology America, Inc., All Rights Reserved 18 Power Wise Low on Power – Low Power Operation Approx. 120 hours Approx. 71 hours Approx. 90 hours M16C, M32C RISC-A Power-saving version RISC-C Power-saving version When continuously operating with two AAA-cell batteries (3 V) V CC = 3V, Xin = 10MHz Battery Battery Operation Approx. 62 days ( 2 months ) Approx. 7.0 days Approx. 2.3 days M16C, M32C RISK-A Power-saving version RISC-C Power-saving version When operating with "super-capacitor" (large-capacity capacitors of about 2 F) and the CPU is restored from wait state every second by a subclock V CC = 3V, Xin = 32KHz Capacitor Ultra-Low Power Operation

© 2008, Renesas Technology America, Inc., All Rights Reserved 21 Summary  Format of Instructions  Distribution of Instruction Execution Cycles  High Speed Operations  Memory Operations  Bit Clear and Bit Set Instructions  Performance to Power Consumption Ratio  Clock Circuit  Low Power Operation  Key Input Interupt