IAY 0600 Digitaalsüsteemide disain Course Overview Alexander Sudnitson Tallinn University of Technology.

Slides:



Advertisements
Similar presentations
Digital System Design Subject Name : Digital System Design Course Code : IT-314.
Advertisements

IAY 0600 Digitaalsüsteemide disain Register Transfer Level Design. FSM Synthesis. Alexander Sudnitson Tallinn University of Technology.
CMSC 611: Advanced Computer Architecture
COE 405 VHDL Basics Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Aiman H. El-Maleh Computer Engineering.
Give qualifications of instructors: DAP
Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi
VHDL Structural Architecture ENG241 Week #5 1. Fall 2012ENG241/Digital Design2 VHDL Design Styles Components and interconnects structural VHDL Design.
EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral,
Chapter 7 Design Implementation (II)
1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
George Mason University ECE 448 – FPGA and ASIC Design with VHDL Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts,
GOOD MORNING.
EENG 2910 – Digital Systems Design Fall Course Introduction Class Time: M9:30am-12:20pm Location: B239, B236 and B227 Instructor: Yomi Adamo
Design methodology.
ECE 332 Digital Electronics and Logic Design Lab Lab 5 VHDL Design Styles Testbenches.
IAY 0600 Digital Systems Design Digitaalsüsteemide disain Course Overview Alexander Sudnitson Tallinn University of Technology.
Shashi Kumar 1 Logic Synthesis: Course Introduction Shashi Kumar Embedded System Group Department of Electronics and Computer Engineering Jönköping Univ.
1 Digital System Design Subject Name : Digital System Design Course Code : IT- 308 Instructor : Amit Prakash Singh Home page :
Principles Of Digital Design Chapter 1 Introduction Design Representation Levels of Abstraction Design Tasks and Design Processes CAD Tools.
Lecture 17 Lecture 17: Platform-Based Design and IP ECE 412: Microcomputer Laboratory.
ADDERS Half Adders Recall that the basic rules of binary addition are as indicated below in Table 2-9. A circuit known as the half-adder carries out these.
IAY 0600 Digitaalsüsteemide disain Register Transfer Level Design (GCD example) Lab. 7 Alexander Sudnitson Tallinn University of Technology.
ENG6090 RCS1 ENG6090 Reconfigurable Computing Systems Hardware Description Languages Part 5: Modeling Structure.
COE 405 Design and Modeling of Digital Systems
FPGA-Based System Design Copyright  2004 Prentice Hall PTR Logic Design Process n Functional/ Non-functional requirements n Mapping into an FPGA n Hardware.
IAY 0600 Digital Systems Design VHDL discussion Dataflow&Behavioral Styles Combinational Design Alexander Sudnitson Tallinn University of Technology.
CWRU EECS 317 EECS 317 Computer Design LECTURE 1: The VHDL Adder Instructor: Francis G. Wolff Case Western Reserve University.
Module 1.2 Introduction to Verilog
Introduction to VHDL Spring EENG 2920 Digital Systems Design Introduction VHDL – VHSIC (Very high speed integrated circuit) Hardware Description.
Fall 2004EE 3563 Digital Systems Design EE 3563 VHSIC Hardware Description Language  Required Reading: –These Slides –VHDL Tutorial  Very High Speed.
1 Hardware Description Languages: a Comparison of AHPL and VHDL By Tamas Kasza AHPL&VHDL Digital System Design 1 (ECE 5571) Spring 2003 A presentation.
IAY 0600 Digital Systems Design VHDL discussion Dataflow Style Combinational Design Alexander Sudnitson Tallinn University of Technology.
VHDL Discussion Finite State Machines
VHDL Discussion Finite State Machines IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology 1.
04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)
Data Flow Modeling in VHDL
IAY 0600 Digital Systems Design Digitaalsüsteemide disain Course Overview Alexander Sudnitson Tallinn University of Technology.
Digital Design Using VHDL and PLDs ECOM 4311 Digital System Design Chapter 1.
IAY 0600 Digital Systems Design Register Transfer Level Design (GCD example) Lab. 7 Alexander Sudnitson Tallinn University of Technology.
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
IAY 0600 Digital Systems Design Timing and Post-Synthesis Verifications Hazards in Combinational Circuits Alexander Sudnitson Tallinn University of Technology.

Introduction to design with VHDL IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology 1.
IAY 0600 Digital Systems Design
Introduction to design with VHDL
16-bit barrel shifter A Mini Project Report
Behavioral Style Combinational Design with VHDL
IAY 0600 Digital Systems Design
IAY 0600 Digital Systems Design
IAY 0600 Digital Systems Design
Behavioral Style Combinational Design with VHDL
RTL Design Methodology
Topics The logic design process..
IAY 0800 Digitaalsüsteemide disain
IAS 0600 Digital Systems Design
Lesson 4 Synchronous Design Architectures: Data Path and High-level Synthesis (part two) Sept EE37E Adv. Digital Electronics.
ECNG 1014: Digital Electronics Lecture 1: Course Overview
ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch
IAS 0600 Digital Systems Design with VHDL
VHDL Introduction.
HIGH LEVEL SYNTHESIS.
IAS 0600 Digital Systems Design
RTL Design Methodology Transition from Pseudocode & Interface
ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL code ECE 448 – FPGA and ASIC Design.
Digital Designs – What does it take
♪ Embedded System Design: Synthesizing Music Using Programmable Logic
EEL4712 Digital Design (VHDL Tutorial).
Presentation transcript:

IAY 0600 Digitaalsüsteemide disain Course Overview Alexander Sudnitson Tallinn University of Technology

2 Administrative Aleksander Sudnitsõn Arvutitehnika instituut, dotsent IT IAY0600 Digitaalsüsteemide disain (erikursus) IAY0600 Digitaalsüsteemide disain (PRAKTIKUM) IAY0120 ARVUTITEHNIKA PROJEKT

3 Administrative Loengute õppetöö keel: inglise Loengud: neljapäeviti Praktikum:IT-307 Dimitri Mihhajlov esemine regulaarne praktikum toimub (pärast registreerimist)

4 Hindamine Teoreetiliste teadmiste osakaal eksamil on 40% hindest ja projekteerimisülesannete tulemuste demonstratsioon koos lahenduste seletuskirjaga annab 60% eksamihindest. “LEARNING BY DOING”

5 Õppeaine sisu lühikirjeldus Digitaalsüsteemide projekteermis-metoodika VHDL ja prgrammeeritava loogika (FPGA) abil. Realiseerimine väliprogrammeeritaval loogikal (FPGA). Digitaalseadmete kiire prototüüpimine. Asünkroonsete süsteemide põhialused (süsteemne vaade).

6 Õppekirjandus Iga tudeng saab komplekti slaide enne loengut. K. L. Short, VHDL for Engineers, Pearson Education, Inc., Sparso J. and Furber S. Principles of Asynchronous Circuit Design: a Systems Perspective. Boston: Kluwer, P.P. Chu, FPGA Prototyping Using VHDL Examples: Xilinx Spartan-3 Version, Jonh, Willey & Sons, J. O. Hamblen, T.S. Hall, and M. D. Furman, Rapid Prototyping of Digital Systems, Springer, 2007.

IAY 0600 Digitaaltehnika erikursus VHDL/PLD Design Methodology Alexander Sudnitson Tallinn University of Technology

8 Digital System A discrete system is a system in which signals have a finite number of discrete values. (This contrasts with analog systems, in which signals have values from an infinite set). Any finite number of discrete values can be represented by a vector of signals with just two values. Such a signal, which takes only two values, is called a digital signal (or binary, or logic), and any device that processes digital signals is called a digital device. Discrete System InputsOutputs

9 Design process The design process consists of obtaining an implementation that satisfies the specification of a system. Specification (behaviour) Analysis (verification)Synthesis Implementation (structure) The analysis of a system has an objective the determination of its specification from an implementation. The synthesis consists of obtaining an implementation that satisfies the specification of a system

10 Different design views Systems can be described from different points of view : Behavior: what does it do? Structure: what is it composed of? Functional properties: how do I interface to it? Physical properties: how fast is it?

11 Design Representation A structural representation is one that the black box as a set of components and their connections. It specifies the product’s implementation without explicit reference to its functionality. In some cases, the functionality could be derived from that of its interconnected components. A behavioral or functional representation is one that looks at the design as a black box. A behavioral representation describes the functionality but not the implementation of a given design, defining the black box’s response to any combination of input values but without describing a way to design or build the black box using the given components. Three different domains of description : A physical representation is one that specifies the physical characteristics of the black box, providing the dimensions and locations of each component and connection contained in the structural description. The physical representation is used to describe the design after it has been manufactured, specifying its weight, size, heat dissipation, power consumption and the position of each input or output pin.

12 Modified Y Chart: levels of abstruction Programmable cores, IPs, ASICs Registers, Adders, Multipliers, etc. Logic netlist, Schematic Boolean equations Dataflow Processes Algorithm Processor, Memory, Peripheral interface View Behavior Description Structural Description Logic Register Transfer (RTL) System Architectural

13 Timing units at different levels Registers, Adders, Multipliers, etc. Logic netlist, Schematic Programmable cores, IPs, ASICs Boolean equations Dataflow Processes Algorithm Processor, Memory, Peripheral interface View Behavior Description Structural Description Delay Clock Cycle Computation Step Comuncation Transaction Time Units

14 Modified Y Chart : this course area Algorithm Processor, Memory, Peripheral interface View Behavior Description Structural Description Registers, Adders, Multipliers, etc. Logic netlist, Schematic Dataflow / RTL Boolean equations Synthesis Analysis

15 Modified Y Chart: transformations Algorithm Processor, Memory, Peripheral interface View Behavior Description Structural Description Registers, Adders, Multipliers, etc. Logic netlist, Schematic Dataflow Boolean equotions Algorithmic Register-Transfer Logic Transformations

16 Chart supporting synthesis activity View Behavior Description Structural Description Algorithmic level of abstraction Register-transfer level of abstraction Logic level of abstraction Behavioral synthesis RTL synthesis Logic synthesis

17 Example: HalfAdder Sum Carry HalfAdder A BStructure Sum = ¬ A&B  A& ¬ B = A  B Carry = A & B ABSumCarry Behavior B Carry  & A Sum

18 Example: HalfAdder Behavioral Description entity HALFADDER is port(A, B: in bit; SUM, CARRY: out BIT); end HALFADDER; Sum = ¬ A&B  A& ¬ B = A  B Carry = A & B HalfAdder A B Sum Carry This is data flow behavioral description architecture RTL of HALFADDER is begin SUM <= A xor B; CARRY <= A and B; end RTL;

19 Design flow for VHDL/PLD design methodology

20 The half-adder UUT and its testbench