MSS, ALICE week, 21/9/041 A part of ALICE-DAQ for the Forward Detectors University of Athens Physics Department Annie BELOGIANNI, Paraskevi GANOTI, Filimon ROUKOUTAKIS, Martha SPYROPOULOU-STASSINAKI (subgroup, of the Greek team, involved in this project)

MSS, ALICE week, 21/9/042 outline Introduction DDL and DATE systems Status and Plans

MSS, ALICE week, 21/9/043 Introduction The Athens group has undertaken the responsibility to work for the DAQ system of the Forward detectors ( FMD, T0, V0) The contribution is related to the DDL and DATE systems of ALICE DAQ.

MSS, ALICE week, 21/9/044 The ALICE data acquisition architecture is as follows: The detectors receive the trigger signals from the Central Trigger Processor (CTP), trough a dedicated Local Trigger Unit (LTU) interfaces to a Timing, Trigger and Control (TTC) system. The readout electronics of all detectors is interfaced to the ALICE standard Detector Data Link (DDL). The data produced by the detectors (event fragments) are injected on the DDLs. At the receiving side of the DDLs there are PCI-based electronic modules, called PCI Readout Receiver Cards (pRORC).The pRORC are hosted by the front-end machines (PCs), which are called Local Data Concentrators (LDC).Each LDC can handle one or more pRORC. The role of the LDCs is to ship the sub-events to a farm of PCs called Global Data Collectors (GDC), where the whole events are built.

MSS, ALICE week, 21/9/045 ALICE DAQ architecture (DATE v4)

MSS, ALICE week, 21/9/046 DAQ architecture (W.Carena) DAQ Network GDC LDC RORC DIU LDC RORC DDL DIU LDC RORC DDL DIU LDC RORC DDL DIU DDL sub-events full events DDL RORC DIU event fragments

MSS, ALICE week, 21/9/047 The ALICE Detector Data Link (DDL) interfaces the Front-End Electronics (FEE) of all sub-detectors to the Read-Out Receiver Cards (RORC) of the data –acquisition system (DAQ). The DDL Source Interface Units (SIU) are connected to the FEEs and placed inside the detector. The DDL Destination Interface Units (DIU) are connected to the RORCs, located in the counting room about 200 meters from the detector. The two DDL interface units are connected through two multi- mode optical fibers. The ALICE DAQ system will contain of about 400 DDLs. The PCI based RORC (pRORC) interfaces the DDL to the PCI bus. It is a 33MHz 32 bits PCI master card which can be used as data collecting device and standalone PCI data source.

MSS, ALICE week, 21/9/048 D etector D ata L ink ( DDL )- Readout system (C.Soos) Front-end electronics Detector Data Links DDL SIU DDL DIU RORC Source Interface Unit Destination Interface Unit Read Out Receiver Card LDC Local Data Concentrator Front- End Digital Crate/Computer P2 Cavern P2 Access shaft Optical Fibre ~200 meters

MSS, ALICE week, 21/9/049 PRORC and DDL in ALICE DAQ

MSS, ALICE week, 21/9/0410 The Athens group has planned to contribute to the run control and on-line monitoring of the forward detectors ( FMD,T0,V0). This project requires the knowledge of the features of the full set of electronic cards of DDL system and, by using the DATE system, to develop the necessary software for the control and monitoring of the transferred data. In Athens, we have a full testing set-up, very similar to the one used by CERN DAQ group for tests and development. For the testing period we are going to use a Front-end emulator card -FEIC- ( instead of detectors’s signal). We are in close collaboration with the CERN DAQ group. One member of our team (F.R.) has attended the special courses ( 6-7/9/2004) organized by the DAQ group at CERN. We are at the stage of loading on a PC all the necessary software ( LINUX, DATE,libraries) and of testing the pRORC card. Soon, we hope, the testing set up will be under control.

MSS, ALICE week, 21/9/0411 The components of DAQ testing set-up in ATHENS {DDL: Detector Data Link} DDL-SIU: Source Interface Unit DDL-DIU: Destination Interface Unit DDL-Optical fibers pRORC: PCI Read-Out Receiver Card FEIC : Front-end Emulator Interface card

MSS, ALICE week, 21/9/0412 Stand-alone use of DDL (E.Denes) RORC DIU RORC PCI Bus SIU DIU RORC PCI Bus Front-End Emulator Interface Card (FEIC)

MSS, ALICE week, 21/9/0413 DDL architecture (C.Soos) Source Interface Unit (SIU) (1) –Interface to the Front-end Electronics (2) Destination Interface Unit (DIU) (3) –Interface to the Readout Receiver Card (4) Full duplex optical link (5) –Multimode optical cable of up to 200 m

MSS, ALICE week, 21/9/0414 Test-event generation LDC Event Building Network GDC Mass Storage Servers RORC DDL Detector readout electronics DDL DIU DDL SIU Front-End Emulator (h/w) RORC Data Generator (f/w) DDL Equipment Data Generator (s/w) Configurable LDC Emulator - COLE (s/w - file) Timer-Rand Equipment Data Generator (s/w)

MSS, ALICE week, 21/9/0415 DATE : Data Acquisition and Test Environment It is a software system that performs data-acquisition activities in a multiprocessor distributed environment. DATE functions --Dataflow( parallel data streams moving independently and concurrently ) --Event building --Load balancing ( Event Distribution Manager, EDM) --Run Control --Online monitoring **Event Dump **Detector analysis (MOOD) --Information logger/browser --Run bookkeeping --Performance monitoring ( AFFAIR) --Test-event generation for tuning and debugging

MSS, ALICE week, 21/9/0416 DATE event builder DATE Event Destribution Manager - (EDM) DATE monitoring Package DATE infoLogger Package DATE databases DATE banks

MSS, ALICE week, 21/9/0417 DDL and DATE installation and tests a)in ATHENS, b)later at CERN Status and Plans Exchange ideas with FWD detector’s experts, in order to collect their requirements for the online monitoring and control Other useful steps for data analysis