Ch. 9 Interrupt Programming and Real-Time Sysstems From Valvano’s Introduction to Embedded Systems

9.1 I/O Synchronization Latency—the time between when the I/O device needs service, and the time when service is initiated. –Hardware Delays –Software Delays

9.1 (cont.) Software Latency (or software response time) –Input Device--The time between new input data ready and the software reading the data. –Output Device—The delay from output device idle and the software giving the device new data to output. –Data Acquisistion—periodic events

9.1 (cont.) Control System Latency —the time between when the control software is suppose to run and when it actually runs. Real Time System —guarantees a worst case latency.

9.1 (CONT.) Throughput (bandwidth)– the maximum data flow in bytes/second that can be processed by the system. Priority —determines the order of service when two or more requests are made at the same time.

9.1 (cont.) Five mechanisms used to synchronize the I/O device with the processor. (Fig. 9.1) –1. Blind Cycle—the software waits a fixed amount of time and assumes that the software will complete before the fixed delay is complete. Example 1—ADC Example 2---Stepper Motor

9.1 (I/O synchronization) 2. Busy Waiting—A software loop that checks the I/O status, waiting for the done state. –Example—ADC with a sequence conversion flag (SCF); read the data after the sequence conversion flag comes on.

9.1 (cont.) 3. Interrupt – uses hardware to cause special software execution. The hardware will request an interrupt when the device has new data to input.

9.1 (cont.) 4. Periodic Polling -- uses a clock interrupt to periodically check the I/O status. 5. DMA – (direct memory access) data is transferred directly from/to memory. –Example– used when high bandwidth and low latency are important.

3 States for Hardware IDLE BUSY (0)—when active (not idle) READY (1)—when active (not idle) See Figure 9.2 (pg. 329) -- The software must wait for the input device to be ready.

9.1 (cont.) Figure 9.1 The input device sets a flag when it has new data. (page 328) Figure 9.2 The software must wait fot the input device to be ready. (page 329). Figure 9.3 The output device sets a flag when it has finished outputting the last data. (page 329). Figure 9.4 The software must wait for the output device to finish the previous operation.

9.2 Interrupt Concepts Interrupt –the automatic transfer of software execution in response to a hardware event that is asynchronous with the current software execution. The hardware event is called a trigger.

9.2.1 Introduction to Interrupts When the hardware needs service (signified by a busy to ready-state transition), an interrupt may be requested by the setting of a trigger flag. Thread– the path of action of software as it executes. Process – the action of software as it executes.

Threads and Processes Threads share access to I/O devices, system resources, and global variables, while processes have separate global variables and system resources—they do not share access to I/O devices. An interrupt occurs if it is armed, triggered, and enabled.

Interrupt Service Routines ISR’s -- the software module that is executed when the hardware requests an interrupt. Polled Interrupts – One large ISR handles all the requests. Vectored Interrupts – Several small ISR’s, specific for every source of interrupt.

Context Switch Context is switched from foreground to background. –1. Current instruction is finished. –2. Execution of the main program is suspended, pushing all registers on the stack. –3. The program counter (PC) is loaded with the address of the ISR. –4. Interrupts are disabled.

After the Context Switch The ISR is executed. Control is returned to the main program.

9.2 Concepts Continued When the interrupt request is accepted, then the execution state will automatically be saved on the stack (CCR, A,B,X,Y and PC). When the service is finished and a return occurs (rti) then the registers will be pulled from the stack.

Definitions Interface Latency—time between when new input is available and the time when the software reads the input data. Device Latency—response time of the external device.

More Definitions Real-Time—A system can guarantee an upper bound (worst case) on latency. An atomic operation is a sequence that once started will always finish, and can not be interrupted.

Checkpoint 9.1 What three conditions must be true for an interrupt to occur? –1) external events occur –2) the condition is armed –3) the microcomputer (interrupt ) is enabled.

Checkpoint 9.2 How do you enable interrupts? –Clear the I bit in the CCR with a cli instruction.

Checkpoint 9.3 What are the steps that occur when an interrupt is processed? –1) Finish the execution. –2) Push registers on the stack. –3) Get interrupt vector. –4) Execute the ISR. –5. Execute the rti instruction returning to the program executing at the time of the interrupt

9.2.2 Essential Components of Interrupt Processing 1) The ability for the hardware to request action from the computer. 2.)The ability for the computer to determine the source (eg. vectored interrupt systems have separate connections to each device and a polled system must poll each device to determine the device.

9.2.2 Essential Components (cont.) 3.)The ability for the computer to acknowledge the interrupt (normally there is a trigger flag that is set that causes the interrupt.)

9.2.3 Sequence of Events 1) Device is armed. 2) Microcomputer interrupts are enabled. 3) An interrupting even occurs that sets the trigger (the context switch or thread switch) NOTE: After the current instruction is complete, it takes 9 more bus cycles on the 9S12 to perform the thread-switch.

9.2.3 Sequence of Events 4) Execution of the ISR. 5) Return control back to the thread that was running. -An rti is run at the end of the ISR. -The stack (containing register values) is pulled.

S12 Interrupts Exceptions include resets, software and hardware interrupts. Each exception has a 16-bit vector pointing to the ISR that handles the exception. These vectors are stored in the upper 128 bytes of standard memory. –(For example, recall the reset pointing to the main program.)

S12 Interrupts (cont.) The vector at a higher address has the priority (hardware priority hierarchy). 6 exceptions are nonmaskable (no associated arm bit, and and the I bit value in the CCR has no affect.) –Power-on-Reset –Clock monitor reset –Computer-Operating Properly (COP) watchdog reset. –Unimplemented instruction (trap) –Software interrupt instruction (swi) –XIRQ signal (if X bit in CCR = 0)

Checkpoint 9.4 What would happen if the ISR forgot to acknowledge the interrupt? –The software would crash, since the ISR would interrupt over and over again.

Checkpoint 9.5 If you did not want to or could not acknowledge the ISR, what else might the ISR do? –The software could disarm.

9.2.4 (cont.) See Table 9.1, page 336

9.2.5 Polled Versus Vectored Interrupts Freescale applies a combination of vectored and polled interrupts. –Vectored—each interrupt source has a uniques address (Table 9.1) –Polled—SCI, SPI, and key wakeup The interrupt sources share the same interrupt address. The ISR software must poll the devices to determine which device needs service.

9.2.6 Pseudo-Interrupt Vectors Some development boards do not allow the erasure and reprogramming of the interrupt vectors. In such systems, vectors can point to “pseudo-interrupt” vectors or memory locations.

9.3 Key Wakeup Interrupts An input connection is configured so an interrupt is requested on either the rising or falling edge of the input.

9.4 Periodic Interrupt Programming Requested on a fixed time basis. –Examples: data acquisition and control systems.

9.5 Real-Time Interrupt (RTI) The RTI can generate interrupts at a fixed rate. –7 bits (RTR6-0) in the RTICTL specify the rate. –Details are on page 343.

9.6 Timer Overflow, Output Compare, and Input Capture 9.6.1Timer Features and Timer Overflow –Timer Overflow can be used to interrupts at a fixed rate Output Compare Interrupts –A third mechanism that can be used to generate periodic interrupts Input Capture Interrupts Input Capture Interrupts –Can be used to measure the period or pulse width of digital signals.

9.7 Pulse Accumulator A mechanism on the 9S12 which can be used to count events, measure frequency, or measure pulse width on a digital input signal.

9.8 Direct Memory Access For high-bandwidth, data goes directly from input to RAM or ROM. Can be used to interface disks or networks. The architecture depends on a co-processor. Devices that support DMA include hard drive controllers on a PC, video graphics on a PC, and the 9S12X series of microcontrollers. See figures 9.12, and 9.13 (page 356)

9.9 Hardware Debugging Tools Tools –Logic Analyzer –In Circuit Emulator (ICE) A hardware debugging tool that recreates the input/output signals of the processor chip. –Background debug module (BDM) can observe software execution in real-time (but is less expensive the an ICE.

9.10 Profiling Profiling, like performance debugging, involves dynamic behavior. Profiling is a debugging process that collects the time history of strategic variables.