May 8, USB 2.0 Electrical Overview Jon Lueker Intel Corporation

May 8, Highlights of the USB 2.0 Electrical Specification w High-speed signaling mode – 480 Mb/s w Existing cables and connectors w Seamless forward/backward compatibility w High-speed functionality smoothly “layered” over existing USB 1.1 w Specifications for each element testable through the use of required test modes

May 8, USB An Extension of USB 1.1 w All the functionality of USB 1.1 w High-speed signaling mode w Protocol for detecting high-speed capability w Protocols for entering/exiting high-speed w Mechanism for disconnect detection w Low-/full-speed specifications tightened, but only for high-speed capable ports w Section 7.2 (“Power Distribution”) specifications unchanged

May 8, USB 2.0 is Interoperable with USB 1.1 w All compliant USB 1.1 devices, hubs, and cables will work with new 2.0 host controllers w USB 2.0 devices and hubs will work with 1.1 host controllers (but not at 480 Mb/s!) w High-speed signaling is supported over compliant USB 1.1 cables and connectors

May 8, Legacy USB Devices (Other than Hubs) w Compliant USB 1.1 devices will generally be USB 2.0 compliant w Exception: Low-speed devices with unshielded, captive cables w USB 2.0 requires foil and drain wire in low-speed captive cables This Is a Compliance Issue – It Doesn’t Affect 1.1/2.0 Interoperability!

May 8, USB 2.0 High-speed Capable Devices w Required to support full-speed signaling w Required to at least enumerate in full-speed w Required to meet tightened full-speed electrical specifications w Must not support low-speed mode It’s Likely That Vendors of High-Speed Capable Devices Will Support Full-Speed Operating Modes ( 250 Million Existing USB 1.1 Ports! )

May 8, USB 2.0 Hubs and Host Controllers w Required to support low, full, and high-speed modes on downstream facing ports w Required to support full-/high-speed on upstream facing ports w Required to support tightened low-/full-speed electrical specifications

May 8, USB 1.1/2.0 Interoperability Matrix 12 Mb/s 1.5 Mb/s USB 2.0 Hub 12 Mb/s 1.5 Mb/s USB 1.1 Hub 480 Mb/s 12 Mb/s 1.5 Mb/s No Hub USB 2.0 Host Controller USB 1.1 Host Controller 12 Mb/s 1.5 Mb/s USB 1.1 Hub 480 Mb/s 12 Mb/s High- Speed Capable Device 12 Mb/s Full-Speed Device 1.5 Mb/s Low- Speed Device USB 2.0 Hub No Hub

May 8, High-Speed Electrical Layer w New signaling w New transceiver elements w New bus states w New low-level protocols w New test modes

May 8, Differential Current Drive R TERM High Speed Signaling Current High Speed Differential Receiver High Speed Differential Receiver High Speed Signaling Current R TERM Data+Data+ Data-Data- High Speed Differential Receiver High Speed Differential Receiver

May 8, Source/Load Terminations w Use of terminations at source and load enable high signal integrity w Reflection coefficient = (RT - Z0) / (RT + Z0) Example: For Z 0 = 52 Ohms and R T = 40 Ohms, reflection coefficient is -13% In the case of a source terminated link, there is a 13% additive/subtractive inter-symbol interference With source and load terminations of 40 Ohms, the effect is reduced to (13%) 2, or 1.7% Double terminations have a similar benefit in reducing the effects of connector and board related discontinuities

May 8, Dual Termination Makes USB 2.0 Speeds Possible on USB 1.X Cable Assemblies USB 2.0 Dual Terminations w Simulation assumes ideal transceivers and terminations w Typical imperfections are modeled for cable, connectors, bond wires, etc. w 2.7X increase in eye opening, 2.7X decrease in jitter Single Termination Dual Termination

May 8, Full-Speed Drivers Provide Terminations w Full-speed drivers asserting SE0 look like resistance to ground w Z DRV + R S = 45 Ohms, +/- 10% w R S may be integrated on-die or placed off-chip High Speed Signaling Current High Speed Signaling Current Data+Data+ Data-Data- RSRSRSRS RSRSRSRS Full Speed Drivers Provide Termination Levels Full Speed Drivers Provide Termination Levels High Speed Differential Receiver High Speed Differential Receiver Z DRV RSRSRSRS RSRSRSRS

May 8, Existing Cables and Connectors w No changes to connector specifications w Cable specs added to USB 1.1 guarantee performance, but pre-ECN cables will support high-speed 250ps 200mV (Worst-Case Simulation)

May 8, DC Coupled w Low-/full-speed modes require DC coupling w DC coupling for high-speed simplifies board design and minimizes cost w Worst case skin-effect losses still leave reliable eye opening w Use of individual ferrite beads on D+ and D- lines no longer possible, but shielded low-speed cable requirement helps a lot No New Magnetics Required for USB 2.0

May 8, High-Speed Signaling Is Only Sensed Differentially Differential + Common Mode = Total Signal High-Speed Driver Generates Differential and Common Mode Components, but Receiver Only Senses Differential Portion

May 8, High-Speed Timing Regenerated in Repeater w High-speed signaling incurs no cumulative jitter or degradation w Bit errors and non-compliant behavior are easily isolated to a single link Low-/full-speed Clock And Data RecoveryClock Recovery ElasticityBufferElasticityBufferDataTransmissionDataTransmission High-speed

May 8, High-Speed Bus States/Levels Amplitude of differential voltage is above Disconnect threshold, due to device terminations being removed Disconnect Current driven to D+ or D- with device terminations absent and D+ pullup enabled ChIRP J, K High-speed signaling levels. Current driven into D+ or D- with terminations present J, K State Amplitude of differential voltage is below Squelch threshold Squelch State Terminations present, but no signaling current being driven Idle State

May 8, USB 2.0 Transceiver Functionality Legacy Driver Disconnection Envelope Detector Single Ended Receivers Legacy Data Receiver LS/FS_Data_Driver_Input Assert_Single_Ended_Zero HS_Differential_Receiver_Output SE_Data+_Receiver_Output SE_Data-_Receiver_Output Rpu_Enable HS_Drive_Enable HS_Data_Driver_Input FS_Edge_Mode_Sel LS/FS_Driver_Output_Enable HS_Current_Source_Enable Differential_Receiver_Enabled HS_Disconnect_Detected Legacy_Differential_Receiver_Output Rs Rs High Speed Current Driver Transmission Envelope Detector HS Differential Data Receiver +3.3V Data+ Data- Rpu

May 8, High-Speed Current Driver w Directing current to ground is fast but wastes power w Turning current on/off saves power but requires settling time w Use of these two options is left to the designer Data + Data - Data + Data - V+ Current Source Enable Current Steering Select 17.78ma

May 8, R PU Switch w When device enters high-speed mode, R PU is disconnected w It is recommended that switching elements be attached to both lines to achieve balanced parasitics

May 8, High-Speed Differential Data Receiver w Required to receive differential signaling with amplitude as small as +/- 200mV w Guideline: Tolerant of common mode voltages from –50mV to +600mV w Reception of data is qualified by envelope detection Data+Data+ Data-Data-

May 8, Transmission Envelope Detector w Must indicate Squelch when differential amplitude is < 100mV w Must indicate !Squelch when differential amplitude is > 150mV w Must incorporate filtering to prevent indication of Squelch during crossover w Should react in less than 4 bit times Differential !Squelch

May 8, Disconnection Envelope Detector w Disconnect threshold detector goes high when signals above disconnect threshold are detected w Output is sampled during last 8 bits of 40 bit uSOF EOP w This prevents spurious disconnect detection in the presence of allowable signaling overshoot Disconnection Threshold Detector Q Q Disconnect Detection D D Clocked During Last Byte of uSOF EOP