Behavioral Buffer Modeling with HSPICE – Intel Buffer 10-08-03 12/4/2002

Objective Demonstrate alternative HSPICE behavioral simulation methods. Can be used when the present features of IBIS models are insufficient. Can be used for pre-silicon feature design characterization in a system environment. Introduction 12/4/2002

Topics Behavioral Driver models Convergence Advisory Close gap between technology and IBIS Convergence Advisory Circuits with that use switches and G elements tend to be more susceptive to convergence problems. High speed differential behavioral buffer and input characterization is an extension of these methods Introduction 12/4/2002

Simple CMOS Model Rp Rn Cn Components: Complementary Pulse source Switch Resistor Capacitor DC source Ground Rn Cn Introduction 12/4/2002

Assignment - 1 Create simple CMOS model Rp=10 ohm, Rn=10 ohms Use Pspice Rp=10 ohm, Rn=10 ohms Adjust Cn to get a 1 ns risetime (20% to 80%) with a 50 ohm load and 1pf tied to ground Hint: Use a 100MHz, 50% duty cycle for the pulse source. Introduction 12/4/2002

Behavioral Model Test Program Start with “testckt” file from pervious class MYBUFF will be our new generator DATAS will modified for different rise and fall times. “DATAS” Printed Wiring Board Data generator package package Buffers Receiver “MYBUF” Introduction 12/4/2002

Level 1 Behavioral Model Vdd Control PWL VCCS 01001100 1.0 V Profile conditioner PWL source Buffer Pad 1.0 V Profile conditioner Math Process to create edges Control PWL VCCS “DATAS” “MYBUF” Vss Introduction 12/4/2002

Data pattern generator Syntax: changed to yield different bit waveforms with different rise and fall times. Introduction 12/4/2002

Bit data waveform Introduction 12/4/2002

Creating a simple equation based V-T wave 01001100 bits pulse(t) The bit pattern is used to create a representative PWL data wave. A proportional unity driving waveform (v-t wave) is created out of the PWL pulse. The edge of the ramp of the PWL pulse is proportional to the time for the bit transition. The entire transition of the pulse is related to the rise/fall time of the wave. Introduction 12/4/2002

Syntax HSPICE for driver The circuit is completed with the voltage profile derived from the unity driving waveform which controls a dependant resistor tied to the n and p loads. In this case the loads are 50 ohms. We need to insure we don’t divide by zero and also do not result in an exact 0 ohm resistance. Introduction 12/4/2002

Convert the n & p resistors to I/V devices The next task is to create I/V subciruits: IVN and IVP To do this we use voltage controlled current source (VCCS) The G element is a piecewise linear (PWL) VCCS To create a I/V device, the control nodes and the output nodes are shorted Introduction 12/4/2002

I/V subcircuit example The columns are voltage on the left and current on the right This forms a table based I/V device since the control voltage imposed and current are across the same nodes Introduction 12/4/2002

If rising and falling edge shape differs, another method is required If the bit pattern is not known a priori, controlling positive and negative shapes independently is difficult. In the previous example we controlled only slew rates not shapes. Will describe how to do this for the 2nd order buffer We will use the pulse source created as homework for the first HSPICE class. The edge for the pulse, if scaled correctly, can be made equal to the time of the bit transition. This is an important concept Introduction 12/4/2002

Level 2 Behavioral Model Block Diagram Bit Pattern P Voltage Profile Generator 1.0 V N Voltage Profile Generator Profile conditioner V-T Control PWL VCCS I-V Vss Vdd Buffer Pad Write enable Dynamic Clamp simplify Introduction 12/4/2002

Voltage- Time Profile Generator Simplify for example Vdd Control PWL VCCS I-V 1.0 V Profile conditioner Fall V-T Write enable Rise Buffer Pad Bit Pattern Voltage- Time Profile Generator V-T Profile conditioner 1.0 V I-V Control PWL VCCS Vss Introduction 12/4/2002

Voltage-Time Profile Generator Rising VT Delay falling edge by falling edge transition time Positive Edge Voltage Profile Generator 1.0 V Voltage controlled voltage source Ramp voltage used to look up output voltage base on v-t table Rising Volt - Time Ramp Generator P Falling Volt - Time Ramp Generator 1.0 V Negative Edge Voltage Profile Generator Data in 1.0 V Falling VT Introduction 12/4/2002

Voltage Time Ramp The voltage-time ramp is a ramp that starts at a specified time and whose voltage is proportional to the time from the specified starting point. In our case, we will create a voltage-time ramp on the detection of each bit edge transition. Introduction 12/4/2002

Explore the voltage across a capacitor If current, I is constant and is equal to the capacitance, then the voltage across the capacitor is equal to time. If the I does not equal C, the voltage is across the capacitor proportional to I/C. Introduction 12/4/2002

Define Characteristics of voltage time ramp relative t=0 Time=t1 V v1=I/C*t1 t A unity voltage time ramp is when I/V = 1 so that t1=v1 Since this voltage is usually small, I/C may be set to 1e9. This means 1 nanosecond corresponds to 1 volt. Introduction 12/4/2002

Circuit to create unit ramp 1 pA 1 pF 1 V The one input of a differential amp is connected to a dc reference and the other input is our input pulse wave. The switch shorts the cap at t=0 and opens when the edge is detected. Introduction 12/4/2002

Delay falling edge .. digitally… well almost Since we will use a threshold detector to determine an edge, we can add signals together and only use the portion of the signal that we deem important. Triggering at the reference threshold delays the negative edge in In delayed S - 2 edge in progress out X Threshold Introduction 12/4/2002

Put the circuit together for positive edge ramp. The processed signal is used to drive the switch which in turn creates the positive edge ramp. 1 pA 1 pF 1 V 1nV = 1 nS after positive edge THRESHOLD_0_1_DETECT in In delayed S - 2 edge in progress out X Introduction 12/4/2002

Put the circuit together for negative edge ramp. The negated data is used to drive the switch which in turn creates the negative edge ramp. in 1 V 1 pA In negated out 1 pF X THRESHOLD_0_1_DETECT 1nV = 1 nS after positive edge Introduction 12/4/2002

Positive Voltage-Time Ramp Generator – HSPICE CODE * delay in by tf Edelay in_delayed 0 DELAY in 0 TD='tf' * create step shaped waveform for delaying by tf Equalify_r edge_in_progress 0 + VOL='V(in)+V(in_delayed)' * switch on edge in progress is above 0.5 v Gswitch_r shunt_c_r 0 + VCR PWL(1) edge_in_progress 0 .5v,.00001 .501v,1g Vone_volt one_volt 0 100v * charge rate is 1v/ns (I/C) Ccharge_r shunt_c_r 0 1pf Icharge_r one_volt shunt_c_r 1ma Introduction 12/4/2002

Negative Voltage-Time Ramp Generator – HSPICE CODE * Create complement of in Eneg_in in_bar 0 vol='1-v(in)' * switch on edge in progress is above 0.5 v Gswitch_f shunt_c_f 0 + VCR PWL(1) in_bar 0 .5v,.00001 .501v,1g * charge rate is 1v/ns (I/C) Ccharge_f shunt_c_f 0 1pf Icharge_f one_volt shunt_c_f 1ma Introduction 12/4/2002

Map ramp to V-T data with By driving the ramp into the control node of equation controlled voltage source, time on the ramp is mapped to voltage. This control voltage ranges from 0v to 1V is geometrically similar to the desired edge relative t=0 V tx=vx t relative t=0 V tx=vx  V(v)=V(t) t Edge rate Introduction 12/4/2002

Mapping with PWL VCVS This is the data for the corresponding edge shape Time is scaled to the edge rate Introduction 12/4/2002

Putting edge together with v-t data Voltage Controlled Voltage Sources Rising V-t curve .SUBCKT VT_RISE_GEN_mid_n in out out_ref Edatar out out_ref PWL(1) in 0 + '0.000*Tr_mid_n' 0.000 + '0.185*Tr_mid_n' 0.006 + '0.315*Tr_mid_n' 0.017 + '0.398*Tr_mid_n' 0.030 ... + '0.917*Tr_mid_n' 0.988 + '0.944*Tr_mid_n' 0.994 + '0.991*Tr_mid_n' 0.999 + '1.000*Tr_mid_n' 1.000 .ENDS VT_RISE_GEN_mid_n Fall time P .SUBCKT VT_FALL_GEN_mid_n in out out_ref Edatar out out_ref PWL(1) in 0 + '0.000*Tf_mid_n' 1.000 + '0.023*Tf_mid_n' 0.996 + '0.034*Tf_mid_n' 0.985 + '0.057*Tf_mid_n' 0.957 + '0.739*Tf_mid_n' 0.016 + '0.773*Tf_mid_n' 0.008 + '0.841*Tf_mid_n' 0.003 + '0.989*Tf_mid_n' 0.000 + '1.000*Tf_mid_n' 0.000 .ENDS VT_FALL_GEN_mid_n Falling V-t curve Introduction 12/4/2002

Behavioral methods can be expanded to include new features Dynamic Clamp Vdd Clamp Voltage Profile Generator 1.0 V Clamp V - T (voltage) Wave 0-1V V Rev Vss + - Control PWL VCCS Clamp V-I Table Profile conditioner Profile conditioner Write enable Buffer Pad Introduction 12/4/2002

Voltage-Time Profile Generator Review Positive V - T (voltage) Wave 0-1V Delay negative edge by negative edge transition time Positive Edge Voltage Profile Generator Positive Volt - Time Ramp Generator V=time after edge 1.0 V Voltage controlled voltage source Ramp voltage used to look up output voltage base on v-t table Caveat: any ramp value > edge time returns 1 volt Bit Pattern P Negative Volt - Time Ramp Generator V=time after edge Negative Edge Voltage Profile Generator 1.0 V Negative V - T (voltage) Wave 0-1V 1.0 V Waveform Voltage Profile* * P profile is the 180 degrees out of phase compared to the N profile Introduction 12/4/2002

Voltage Profile Resistance Conditioner Riv Vout Rvt Goal: Create V-T Profile that produces a geometrically similar waveform at Vout Limitation: Loads need in the range of Rtcal Voltage controlled resistor Rtcal Introduction 12/4/2002

Assignment 2– Create HSPICE Buffer Model Rp = 100 ohms, Rn=10 ohms Rise time 20%-80% 1.5 ns when driving a 50 ohms load ground You need to adjust the pulse transition time You should use sweep results in you report. Use wave shape as follows '(1-exp(-1*(pwr(abs(v(in))*2.4,wf))))' wf=2, v(in) is pulse wave Vcc = 2.5 V, Vss = 0 V Check simulation against calculations of Vol and Voh with 50 ohm to Vss load Introduction 12/4/2002

Key Techniques To Remember Unity time voltage ramp PWL Voltage control voltage source creates V(t) edges. Simple buffers can be created by using switches in place of voltage controlled resistors. Introduction 12/4/2002