Work in Progress --- Not for Publication 26 April Interconnect Working Group ITRS April 2001 Grenoble

Work in Progress --- Not for Publication 26 April Attendees Hans Barth - Europe Joaquin Torres - Europe Hyun Chul Sohn - Korea Ahihiko Ohsaki - Japan R Aoki - Japan C Case - US

Work in Progress --- Not for Publication 26 April Agenda Section updates: –Conductors –Dielectrics –Planarizaation –Etch –Reliability –System and performance –SOC

Work in Progress --- Not for Publication 26 April Agenda contd. Crosscut updates: –Modeling and simulations –Defect reduction –Metrology –ESH –Design

Work in Progress --- Not for Publication 26 April Nucleation/Conductors update Expanded description of ALD Spin etch planarization (CEP) (metal) Cu ECD combined with planarization Need for novel/potential cleans –Conductors, etch, dielectrics and planarization Reconciliation of new node info with wiring data

Work in Progress --- Not for Publication 26 April Wiring updates

Work in Progress --- Not for Publication 26 April Nucleation/Conductors update Expanded treatment of opto/electrical on chip materials needs –in System and Performance sections Add doped Cu conductors –unknown impact on resistivity vs dimension –allows higher current density, accommodates higher wire temp at local/inter levels Changed Cu resistivity for global wires (2.2 cm) New intermediate/local wiring Cu conductivity

Work in Progress --- Not for Publication 26 April Dielectrics update To address confusion on definition of effective k –add text that effective k includes all integration needs including cap, etch stops, hard masks Adding physical metrics on mechanical properties of porous materials from models so that text can support issues of using these weak materials options such as composites, fiber reinforcement included in text May add high k Tech Requirement k metric –material must meet temperature budget –still under consideration

Work in Progress --- Not for Publication 26 April Dielectrics update Add thermal properties –still under discussion Model effective k calculation that also includes crosstalk –with and without trench etch stop Photoresist poisoning of low k materials - text

Work in Progress --- Not for Publication 26 April Planarization update More detailed discussion of CEP Schematic and calculation for new dishing/erosion/thinning metrics Porous low k will require either alternative planarization or stopping layer/structural enhancements to be compatible with existing planarization techniques - text Addressing planarization of thick metal for inductors

Work in Progress --- Not for Publication 26 April Etch update New Potential Solutions figure –Distinguished by level and function –MRAM, FERAM –passives –De-emphasize HDP Etch is now driven by new materials and integration schemes Etch section - includes potential solutions with and without etch stops

Work in Progress --- Not for Publication 26 April System and Performance update Including resistivity increase (change) in performance calculations Agreement on current density - all regions agree 04/01 Include Raphael calculation and schematic for low k scenarios - for effective k and crosstalk Include in appendix some references on process variability effect on performance

Work in Progress --- Not for Publication 26 April SOC update Expanded detail on passives - create new technology requirements –thick metal thickness for inductors –Fe cores –Resistors –Capacitance per unit area metric - fF/micron 2 –Q factor

Work in Progress --- Not for Publication 26 April Cross Thrust ESH Chemicals, Materials and Equipment Management –add reuse and recycle for CMP and ECD –ULV chemical dispense Climate Change Mitigation –add PFC POU abatement Workplace Protection –address ClF 3, VOC from low k and POU abatement, PM schemes for hazardous chambers Resource Conservation –Alternative clean gases –Cu waste (CMP plus ECD) and water reclaim

Work in Progress --- Not for Publication 26 April Cross Thrust Metrology Dielectrics –porosity - size, distribution etc max pore diameter 10% of spacing average pore size 5% +- 3 sigma of spacing –k anisotropy - edge effects, - text Interfacial issues - contact to high k - text Conductors –voids - adding metric similar to dielectric but using metal half pitch –Cu ECD bath metrology - CVS, etc. Planarization –which of the new Technology Requirements need new metrology? –Cross section feature volume per unit length

Work in Progress --- Not for Publication 26 April Cross Thrust Metrology Etch –3DCD sidewall CD, possibly post planarization trench bottom profile –diagnostics for run to run stability –end point for low k (etch stops) –High A/R contacts (DRAM) - 3DCD endpoint for contact SoC –High k measurements - thickness, composition, k non-uniformity –R and L measurements - thick metal thickness

Work in Progress --- Not for Publication 26 April Cross Thrust Design Crosstalk metric - also Modeling Review the resistivity vs wiring level quandry - also modeling Capacitance per unit area metric - fF/micron 2 Q factor

Work in Progress --- Not for Publication 26 April Cross Thrust Modeling Crosstalk metric Review the resistivity vs wiring level quandry - also modeling Capacitance per unit area metric - fF/micron 2 Q factor

Work in Progress --- Not for Publication 26 April Cross Thrust PIDS Al on Cu for bonding pad Joe Adam had these problems Operating temp for harsh environments MEMS and interconnect Embedded epi in interconnect - possibly compound semi for emitter/receiver pairs

Work in Progress --- Not for Publication 26 April Cross Thrust Modeling Thermomechanical simulations issues request to modeling Thermal cycling in operation for multi-level structures Stress voiding Crosstalk at cell and higher effects, steadystate and operating

Work in Progress --- Not for Publication 26 April Difficult Challenges New materials Reliability Process integration Dimensional control Interconnect process with low/no device impact New materials and size effects Process complexity 3DCD Aspect ratios for fill and etch Solutions beyond copper and low Long termNear term

Work in Progress --- Not for Publication 26 April Remaining issues Adequate treatment of Cu resistivity impacts Need to agree on number of interconnect levels with respect to global wiring Proposed structural changes to potential solutions table