Design Technical Working Group 4 April 2003 - Work In Progress – Not for Publication Design Technical Working Group Spring Meeting 2003 uUS oAndrew Kahng,

Slides:

Advertisements

Similar presentations

ITRS Test TWG Don Edenfeld April 20 th, 2004 Spring Workshop - Stressa, Italy.

Advertisements

RF and A/MS Technologies for Wireless Communications Working Group 2 April Work In Progress – Not for Publication 1 PIDS ITWG RF and A/MS Technologies.

2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Design ITWG ITRS-2003 December 2, 2003 Taiwan Japan: Ichiro Yamamoto, Tamotsu Hiwatashi Taiwan:

ITRS Design + System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes Shireesh Verma.

SoC Challenges & Transaction Level Modeling (TLM) Dr. Eng. Amr T. Abdel-Hamid ELECT 1002 Spring 2008 System-On-a-Chip Design.

TOPIC : SYNTHESIS DESIGN FLOW Module 4.3 Verilog Synthesis.

1 General-Purpose Languages, High-Level Synthesis John Sanguinetti High-Level Modeling.

SOC Design: From System to Transistor

OBJECTIVES Learn the history of HDL Development. Learn how the HDL module is structured. Learn the use of operators in HDL module. Learn the different.

EECE **** Embedded System Design

ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.

ECE Synthesis & Verification - Lecture 2 1 ECE 667 Spring 2011 ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits High-Level (Architectural)

Winter-Spring 2001Codesign of Embedded Systems1 Introduction to SystemC Part of HW/SW Codesign of Embedded Systems Course (CE )

Chapter 1 : SystemC Overview. What is SystemC Systemc is a modeling platform  A set C++ class library to add hardware modeling constructs  Simulation.

Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi

Evolution and History of Programming Languages Software/Hardware/System.

Consortium The Organization Overview & Status Update February 2006 Ralph von Vignau, The SPIRIT Consortium Chair © SPIRIT All rights reserved.

The Design Process Outline Goal Reading Design Domain Design Flow

Design For Verification Synopsys Inc, April 2003.

Presenter : Yeh Chi-Tsai System-on-chip validation using UML and CWL Qiang Zhu 1, Ryosuke Oish 1, Takashi Hasegawa 2, Tsuneo Nakata 1 1 Fujitsu Laboratories.

1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral,

Copyright  2006 Daniel D. Gajski 1 Extreme Makeover of System Design Science Daniel Gajski Center for Embedded Computer Systems (CECS) University of California,

Copyright  1999 Daniel D. Gajski IP – Based Design Methodology Daniel D. Gajski University of California

ITRS-2001 Design ITWG Plan December 6, 2000 Bill Joyner, SRC/IBM.

Digital System Design Verilog ® HDL Maziar Goudarzi.

ECE 699: Lecture 2 ZYNQ Design Flow.

ELEN468 Lecture 11 ELEN468 Advanced Logic Design Lecture 1Introduction.

Embedded Systems Design at Mentor. Platform Express Drag and Drop Design in Minutes IP Described In XML Databook s Simple System Diagrams represent complex.

(1) Introduction © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.

I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

Chap. 1 Overview of Digital Design with Verilog. 2 Overview of Digital Design with Verilog HDL Evolution of computer aided digital circuit design Emergence.

CAD Techniques for IP-Based and System-On-Chip Designs Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {

Principles Of Digital Design Chapter 1 Introduction Design Representation Levels of Abstraction Design Tasks and Design Processes CAD Tools.

CAD for Physical Design of VLSI Circuits

ASIC/FPGA design flow. FPGA Design Flow Detailed (RTL) Design Detailed (RTL) Design Ideas (Specifications) Design Ideas (Specifications) Device Programming.

Foundation Express The HDL Value Leader. Xilinx Foundation Express The HDL Value Leader  Complete HDL Development Environment Best in Class EDA Tools.

Copyright © 2002 Qualis Design Corporation Industry and Textbook Overview Qualis Design Corporation PO Box 4444 Beaverton, Oregon USA Phone:

1 H ardware D escription L anguages Modeling Digital Systems.

COE 405 Design and Modeling of Digital Systems

Chonnam national university VLSI Lab 8.4 Block Integration for Hard Macros The process of integrating the subblocks into the macro.

ESL and High-level Design: Who Cares? Anmol Mathur CTO and co-founder, Calypto Design Systems.

ASIC, Customer-Owned Tooling, and Processor Design Nancy Nettleton Manager, VLSI ASIC Device Engineering April 2000 Design Style Myths That Lead EDA Astray.

1 IMEC / KHBO June 2004 Micro-electronics SystemC Dorine Gevaert.

2D/3D Integration Challenges: Dynamic Reconfiguration and Design for Reuse.

An Overview of Hardware Design Methodology Ian Mitchelle De Vera.

1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral,

IMPLEMENTATION OF MIPS 64 WITH VERILOG HARDWARE DESIGN LANGUAGE BY PRAMOD MENON CET520 S’03.

M.Mohajjel. Digital Systems Advantages Ease of design Reproducibility of results Noise immunity Ease of Integration Disadvantages The real world is analog.

VLSI Design System-on-Chip Design

Introduction to ASIC flow and Verilog HDL

ZHAO(176/MAPLD2004)1 FFT Mapping on Mathstar’s FPOA FilterBuilder Platform MathStar, Inc. Sept 2004.

1 A hardware description language is a computer language that is used to describe hardware. Two HDLs are widely used Verilog HDL VHDL (Very High Speed.

SUBJECT : DIGITAL ELECTRONICS CLASS : SEM 3(B) TOPIC : INTRODUCTION OF VHDL.

EMT 351/4 DIGITAL IC DESIGN Week # 1 EDA & HDL.

System-on-Chip Design

ASIC Design Methodology

Digital System Design An Introduction to Verilog® HDL

Xilinx Ready to Use Design Solutions

Chips4Makers Toolchain

IP – Based Design Methodology

A Review of Processor Design Flow

ITRS Roadmap Design Process Open Discussion EDP 2001

Hardware Description Languages

Modeling Languages and Abstract Models

ECE 699: Lecture 3 ZYNQ Design Flow.

VHDL Introduction.

HIGH LEVEL SYNTHESIS.

Design Methodology & HDL

Chapter 10 Introduction to VHDL

VHDL Synthesis for Implementing Digital Designs into FPGAs

Presentation transcript:

Design Technical Working Group 4 April Work In Progress – Not for Publication Design Technical Working Group Spring Meeting 2003 uUS oAndrew Kahng, UC San Diego (Telephone) uJapan oYamamoto-san (Telephone) uEurope oRalf Brederlow, Infineon oMaarten Vertregt, Philips oJosef Sauerer, FhG oPeter Schwarz, FhG

Design Technical Working Group 4 April Work In Progress – Not for Publication Revisions for ITRS 2003 System Drivers Chapter –New material Embedded memory sub-chapter –Improvements to existing material SOC-centric chapter reorganization include SIP in multi technology integration timeline Design Chapter –Seamless design flow (System and Circuit EDA including AMS and other styles for SoC/SiP design) –Refinement of design cost model –Prepare Revision of Design Chapter (treat issues once, align with System Drivers Chapter)

Design Technical Working Group 4 April Work In Progress – Not for Publication x = a + b + c + d + e + f + g + h + i ; Higher Level of Abstraction Define # of Adders and Order of Calculation Constraint = Power, Speed, Area RTL (Less productive but more exact) Result A # of Adders = 1 Speed = 9 Clocks Result B # of Adders = 2 Speed = 5 Clocks RTL Synthesis will automate the RTL design task. Example: dealing with Productivity Gap

Design Technical Working Group 4 April Work In Progress – Not for Publication Example: System and Circuit EDA for AMS Executable specification, A/MS description languages: VHDL-AMS, Verilog-AMS, SystemC-AMS, … Circuit synthesis Design validation: simulation and formal verification Layout synthesis, incl. RF and interconnect-driven Design for manufacturability, yield enhancement IP re-use