Chapter 9 Finite-State Machines 4/22/2017 Chapter 9 Finite-State Machines Finite-state machine background Writing VHDL for a FSM FSM initialization FSM flipflop output signal FSM synthesis Exercise Slides 2-9 based on: Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis 22-Apr-17 EE514 EE514

Introduction Describing embedded system’s processing behavior 4/22/2017 Introduction Describing embedded system’s processing behavior Can be extremely difficult Complexity increasing with increasing IC capacity Past: washing machines, small games, etc. Hundreds of lines of code Today: TV set-top boxes, Cell phone, etc. Hundreds of thousands of lines of code Desired behavior often not fully understood in beginning Many implementation bugs due to description mistakes/omissions English (or other natural language) common starting point Precise description difficult to impossible Example: Motor Vehicle Code – thousands of pages long... 22-Apr-17 EE514 EE514

An example of trying to be precise in English 4/22/2017 An example of trying to be precise in English California Vehicle Code Right-of-way of crosswalks (b) The provisions of this section shall not relieve a pedestrian from the duty of using due care for his or her safety. No pedestrian shall suddenly leave a curb or other place of safety and walk or run into the path of a vehicle which is so close as to constitute an immediate hazard. No pedestrian shall unnecessarily stop or delay traffic while in a marked or unmarked crosswalk. 21950. (a) The driver of a vehicle shall yield the right-of-way to a pedestrian crossing the roadway within any marked crosswalk or within any unmarked crosswalk at an intersection, except as otherwise provided in this chapter. (c) The provisions of subdivision (b) shall not relieve a driver of a vehicle from the duty of exercising due care for the safety of any pedestrian within any marked crosswalk or within any unmarked crosswalk at an intersection. All that just for crossing the street (and there’s much more)! How can we (precisely) capture behavior? 22-Apr-17 EE514 EE514

Introductory example: An elevator controller 4/22/2017 Introductory example: An elevator controller Simple elevator controller Request Resolver resolves various floor requests into single requested floor Unit Control moves elevator to this requested floor buttons inside elevator Unit Control b1 down open floor ... Request Resolver up/down buttons on each b2 bN up1 up2 dn2 dnN req up System interface up3 dn3 “Move the elevator either up or down to reach the requested floor. Once at the requested floor, open the door for at least 10 seconds, and keep it open until the requested floor changes. Ensure the door is never open while moving. Don’t change directions unless there are no higher requests when moving up or no lower requests when moving down…” Partial English description 22-Apr-17 EE514 EE514

Finite-state machine (FSM) model 4/22/2017 Finite-state machine (FSM) model Trying to capture this behavior as sequential program is a bit awkward Instead, we might consider an FSM model, describing the system as: Possible states E.g., Idle, GoingUp, GoingDn, DoorOpen Possible transitions from one state to another based on input E.g., req > floor Actions that occur in each state E.g., In the GoingUp state, u,d,o,t = 1,0,0,0 (up = 1, down, open, and timer_start = 0) Try it... 22-Apr-17 EE514 EE514

Finite-state machine (FSM) model 4/22/2017 Finite-state machine (FSM) model Idle GoingUp req > floor req < floor !(req > floor) !(timer < 10) DoorOpen GoingDn u,d,o, t = 1,0,0,0 u,d,o,t = 0,0,1,0 u,d,o,t = 0,1,0,0 u,d,o,t = 0,0,1,1 u is up, d is down, o is open req == floor !(req<floor) timer < 10 t is timer_start UnitControl process using a state machine 22-Apr-17 EE514 EE514

Formal definition An FSM is a 6-tuple F<S, I, O, F, H, s0> 4/22/2017 Formal definition An FSM is a 6-tuple F<S, I, O, F, H, s0> S is a set of all states {s0, s1, …, sl} I is a set of inputs {i0, i1, …, im} O is a set of outputs {o0, o1, …, on} F is a next-state function (S x I → S) H is an output function (S → O) s0 is an initial state Moore-type Associates outputs with states (as given above, H maps S → O) Mealy-type Associates outputs with transitions (H maps S x I → O) Shorthand notations to simplify descriptions Implicitly assign 0 to all unassigned outputs in a state Implicitly AND every transition condition with clock edge (FSM is synchronous) 22-Apr-17 EE514 EE514

4/22/2017 Formal definition 22-Apr-17 EE514 EE514

Describing a system as a finite state machine 4/22/2017 Describing a system as a finite state machine 1. List all possible states 2. For each state, list possible transitions, with conditions, to other states 3. For each state and/or transition, list associated actions req > floor !(req > floor) 4. For each state, ensure exclusive and complete exiting transition conditions No two exiting conditions can be true at same time Otherwise nondeterministic state machine One condition must be true at any given time Reducing explicit transitions should be avoided when first learning u,d,o, t = 1,0,0,0 u,d,o,t = 0,0,1,0 u,d,o,t = 0,1,0,0 u,d,o,t = 0,0,1,1 Idle GoingUp DoorOpen GoingDn req < floor req > floor req == floor !(timer < 10) timer < 10 req < floor !(req<floor) u is up, d is down, o is open t is timer_start 22-Apr-17 EE514 EE514

Consider FSM transition diagram 4/22/2017 Writing VHDL for a FSM Consider FSM transition diagram 22-Apr-17 EE514 EE514

4/22/2017 Writing VHDL for a FSM Use case statement to describe the combinational circuit and a clock sensitive process to infer flip-flops use IEEE.std_logic_1164.all; entity RWCNTL is port( CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic); end RWCNTL; architecture RTL of RWCNTL is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; begin comb : process (CURRENT_STATE, START, RW, LAST) DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; 22-Apr-17 EE514 EE514

Writing VHDL for a FSM case CURRENT_STATE is when IDLE => 4/22/2017 Writing VHDL for a FSM case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then NEXT_STATE <= WAITING; when WRITING => WRSIG <= '1'; 22-Apr-17 EE514 EE514

Writing VHDL for a FSM if LAST = '0' then NEXT_STATE <= WRITING; 4/22/2017 Writing VHDL for a FSM if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; NEXT_STATE <= IDLE; end case; end process; seq : process begin wait until CLOCK'event and CLOCK = '1'; CURRENT_STATE <= NEXT_STATE; end RTL; 22-Apr-17 EE514 EE514

4/22/2017 Writing VHDL for a FSM 22-Apr-17 EE514 EE514

4/22/2017 Writing VHDL for a FSM 22-Apr-17 EE514 EE514

Performance of FSM Similar to regular sequential circuit 22-Apr-17 4/22/2017 Performance of FSM Similar to regular sequential circuit 22-Apr-17 EE514 EE514

4/22/2017 Sample timing diagram 22-Apr-17 EE514 EE514

4/22/2017 State assignment State assignment: assign binary representations to symbolic states In a synchronous FSM All assignments work Good assignment reduce the complexity of next-state/output logic Typical assignment Binary, Gray, one-hot, almost one-hot 22-Apr-17 EE514 EE514

4/22/2017 State assignment 22-Apr-17 EE514 EE514

4/22/2017 FSM initialization To asynchronously reset FSM add if statement which includes elseif with rising edge of the clock library IEEE; use IEEE.std_logic_1164.all; entity RWCNTLR is port( RESETn : in std_logic; CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic); end RWCNTLR; architecture RTL of RWCNTLR is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; begin comb : process(CURRENT_STATE, START, RW, LAST) DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; 22-Apr-17 EE514 EE514

FSM initialization case CURRENT_STATE is when IDLE => 4/22/2017 FSM initialization case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then NEXT_STATE <= WAITING; when WRITING => WRSIG <= '1'; if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; NEXT_STATE <= IDLE; end case; end process; seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; elsif (CLOCK'event and CLOCK = '1') then CURRENT_STATE <= NEXT_STATE; end RTL; 22-Apr-17 EE514 EE514

4/22/2017 FSM initialization 22-Apr-17 EE514 EE514

FSM initialization To infer a synchronous reset use if statement 4/22/2017 FSM initialization To infer a synchronous reset use if statement before case statement in the combinational part library IEEE; use IEEE.std_logic_1164.all; entity RWCNTLR1 is port( RESETn : in std_logic; CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic); end RWCNTLR1; architecture RTL of RWCNTLR1 is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; begin comb : process(RESETn, CURRENT_STATE, START, RW, LAST) DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; if (RESETn = '0') then NEXT_STATE <= IDLE; else 22-Apr-17 EE514 EE514

FSM initialization case CURRENT_STATE is if LAST = '0' then 4/22/2017 FSM initialization case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then NEXT_STATE <= WAITING; when WRITING => WRSIG <= '1'; if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; NEXT_STATE <= IDLE; end case; end process; seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; elsif (CLOCK'event and CLOCK = '1') then CURRENT_STATE <= NEXT_STATE; end RTL; 22-Apr-17 EE514 EE514

4/22/2017 FSM initialization 22-Apr-17 EE514 EE514

FSM flip-flop output signal 4/22/2017 FSM flip-flop output signal To have outputs driven by flip-flops use output signal assignment in the process under rising edge of the clock library IEEE; use IEEE.std_logic_1164.all; entity RWCNTLRF is port( RESETn : in std_logic; CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic); end RWCNTLRF; architecture RTL of RWCNTLRF is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; signal DONE_comb, RDSIG_comb, WRSIG_comb : std_logic; begin comb : process(CURRENT_STATE, START, RW, LAST) DONE_comb <= '0'; RDSIG_comb <= '0'; WRSIG_comb <= '0'; 22-Apr-17 EE514 EE514

FSM flip-flop output signal 4/22/2017 FSM flip-flop output signal case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG_comb <= '1'; if LAST = '0' then NEXT_STATE <= WAITING; when WRITING => WRSIG_comb <= '1'; if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE_comb <= '1'; NEXT_STATE <= IDLE; end case; end process; seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; elsif (CLOCK'event and CLOCK = '1') then CURRENT_STATE <= NEXT_STATE; DONE <= DONE_comb; 22-Apr-17 EE514 EE514

FSM flipflop output signal 4/22/2017 FSM flipflop output signal Note that synthesized circuit has 3 more latches RDSIG <= RDSIG_comb; WRSIG <= WRSIG_comb; end if; end process; end RTL; 22-Apr-17 EE514 EE514

Note that synthesized circuit has 3 more latches 4/22/2017 Comparing to the original design the output signals are latched at the next clock edge Note that synthesized circuit has 3 more latches 22-Apr-17 EE514 EE514

FSM flipflop output signal 4/22/2017 FSM flipflop output signal This code can be simplified if the case statement is included inside if statement in the seq process temporary signals are avoided and simulation runs faster architecture COMBINED of RWCNTLRF is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE : STATE_TYPE; begin seq : process (CLOCK, RESETn) if (RESETn = '0') then CURRENT_STATE <= IDLE; DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; elsif (CLOCK'event and CLOCK = '1') then 22-Apr-17 EE514 EE514

FSM flipflop output signal 4/22/2017 FSM flipflop output signal case CURRENT_STATE is when IDLE => if START = '0' then CURRENT_STATE <= IDLE; elsif RW = '1' then CURRENT_STATE <= READING; else CURRENT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then CURRENT_STATE <= WAITING; when WRITING => WRSIG <= '1'; if LAST = '0' then CURRENT_STATE <= WRITING; else CURRENT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; CURRENT_STATE <= IDLE; end case; end process; end COMBINED; 22-Apr-17 EE514 EE514

FSM synthesis Some synthesis tools can synthesize the FSMs. 4/22/2017 FSM synthesis Some synthesis tools can synthesize the FSMs. They usually generate better results than a general synthesis from VHDL code. It is better for an FSM to be an independent block (VHDL code). This makes the synthesis process easier, especially in writing synthesis constraints, encoding states, and synthesis commands. 22-Apr-17 EE514 EE514

To Create a State Diagram 4/22/2017 To Create a State Diagram Select New Source on the Project menu. Select State Diagram from the list in the dialog box. Enter a name for the new state diagram. Enter a directory in which the state diagram will reside. Click Next. Click Finish. The StateCAD program displays. Select Design Wizard on the File menu in StateCAD. Click Save File Click the Generate HDL button. Close StateCAD. Click Add Source on the Project menu to add the state diagram .dia file and the HDL module to your ISE project. 22-Apr-17 EE514 EE514

4/22/2017 FSM 22-Apr-17 EE514 EE514

4/22/2017 FSM 22-Apr-17 EE514 EE514

4/22/2017 FSM 22-Apr-17 EE514 EE514

Synthesized FSM 22-Apr-17 EE514 4/22/2017 -- -- File: D:\FDNTN\ACTIVE\PROJECTS\FSM\fsm1.vhd -- created: 10/25/99 23:08:10 -- from: 'D:\FDNTN\ACTIVE\PROJECTS\FSM\fsm1.asf' -- by fsm2hdl - version: 2.0.1.52 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library SYNOPSYS; use SYNOPSYS.attributes.all; entity fsm1 is port (clock: in STD_LOGIC; last: in STD_LOGIC; rw: in STD_LOGIC; start: in STD_LOGIC; done: out STD_LOGIC; rdsig: out STD_LOGIC; wrsig: out STD_LOGIC); end; architecture fsm1_arch of fsm1 is -- SYMBOLIC ENCODED state machine: Sreg0 type Sreg0_type is (idle, reading, waiting, writing); signal Sreg0: Sreg0_type; begin --concurrent signal assignments --diagram ACTIONS; Sreg0_machine: process (clock) if clock'event and clock = '1' then case Sreg0 is when idle => if rw='0' then Sreg0 <= writing; elsif start='0' then Sreg0 <= idle; elsif rw='1' then Sreg0 <= reading; end if; when reading => if last='0' then elsif last='1' then Sreg0 <= waiting; 22-Apr-17 EE514 EE514

Synthesized FSM when waiting => Sreg0 <= idle; 4/22/2017 Synthesized FSM when waiting => Sreg0 <= idle; when writing => if last='0' then Sreg0 <= writing; elsif last='1' then Sreg0 <= waiting; end if; when others => null; end case; end process; -- signal assignment statements for combinatorial outputs rdsig_assignment: rdsig <= '1' when (Sreg0 = reading and last='0') else '1' when (Sreg0 = reading and last='1') else '1'; done_assignment: done <= '1' when (Sreg0 = waiting) else wrsig_assignment: wrsig <= '1' when (Sreg0 = writing and last='0') else '1' when (Sreg0 = writing and last='1') else end fsm1_arch; 22-Apr-17 EE514 EE514

StateCAD Translates state diagrams to HDL based designs 4/22/2017 StateCAD Translates state diagrams to HDL based designs Automatically analyzes designs for problems such as Stuck-at states Conflicting state assignments Indeterminate conditions Includes StateBench 22-Apr-17 EE514 EE514

StateCAD Support concurrent state machines 4/22/2017 StateCAD Support concurrent state machines Graphical operators for states Mealy & Moore outputs Resets Combinatorial and synchronous logic Text comments 22-Apr-17 EE514 EE514

4/22/2017 FSM Wizard in StateCAD 22-Apr-17 EE514 EE514

Logic Wizard in StateCAD 4/22/2017 Logic Wizard in StateCAD StateCAD Logic Wizard for data flow structures Shifters, registers,latches, counters, muxes, etc. Requires object type, attributes, and signal names Handles boolean equations within the wizard 22-Apr-17 EE514 EE514

Overview StateCAD diagrams have .dia extensions StateCAD output 4/22/2017 Overview StateCAD diagrams have .dia extensions File names have an eight character limit StateCAD output Language specific files VHDL, Verilog, or ABEL VHDL and Verilog output files can be compiled using various tools Exemplar Synopsys 22-Apr-17 EE514 EE514

Beginning a Diagram Project  New Source State Diagram File Name 4/22/2017 Beginning a Diagram Project  New Source State Diagram File Name 22-Apr-17 EE514 EE514

Adding States In the Draw Mode tool bar, use the State Mode command 4/22/2017 Adding States In the Draw Mode tool bar, use the State Mode command States are given unique names when they are added or copied May be used as actual state names Can be changed or edited Syntax of states: NAME OUTPUTS=1; NAME_ONLY 22-Apr-17 EE514 EE514

BUSOUT = (sigA OR sigB) AND NOT(sigC OR sigD) 4/22/2017 Outputs Output list contains equations Output equations State variables Outputs support complex data flow logic Bit or vector equations Counters Muxes Example: NAME CNTR <= CNTR + 1; BUSOUT = (sigA OR sigB) AND NOT(sigC OR sigD) 22-Apr-17 EE514 EE514

Outputs Output Wizard is the easiest way to add outputs 4/22/2017 Outputs Output Wizard is the easiest way to add outputs In Edit State (double-click on a state), select the Output Wizard button 22-Apr-17 EE514 EE514

4/22/2017 Transitions Use the Transition button to draw curved and straight transitions: Straight transitions: Click on one state, then click on another state Curved transitions: Click on one state (a small square appears), another small square will follow the cursor (click to place), one more square will appear, place the final square on the state destination 22-Apr-17 EE514 EE514

Curved Transitions Multiple segment transitions 4/22/2017 Curved Transitions Multiple segment transitions Enable through Options menu  Graphics Deselect “Single Segment Curve” Unlimited number of segments Each segment contains a starting point, two control points, and an endpoint 22-Apr-17 EE514 EE514

Transition Conditions 4/22/2017 Transition Conditions To add a transition condition, double-click on the transition for the Edit Condition dialog box Conditions are Boolean equations Syntax errors and indeterminate conditions are checked during compilation Conditions may use inputs, outputs, and logic variables State names and variables from one machine may be used in the condition of another machine. This allows communication between state machines 22-Apr-17 EE514 EE514

Reset Reset is taken from any state, when its condition is true 4/22/2017 Reset Reset is taken from any state, when its condition is true One synchronous and one asynchronous reset are allowed per state machine Reset condition should not contain variables used in any other transition of the state machine Reset overrides the state transition conditions 22-Apr-17 EE514 EE514

Reset Use the Reset Mode command: 4/22/2017 Reset Use the Reset Mode command: Click on an empty region for your start point Click on the desired reset state You will automatically be asked to select the mode (asynchronous or synchronous) The condition is automatically added (Reset) 22-Apr-17 EE514 EE514

4/22/2017 Text and Comments To add text and comments to state diagrams, use the Text Mode: Enter text here Add as comments to HDL code Make attributes visible 22-Apr-17 EE514 EE514

4/22/2017 Text and Comments Test vectors added into the HDL and included files can be referenced by including text in HDL Language specific logic not supported by StateCAD may be implemented Caution: When adding comments in HDL, text lines may be broken by StateCAD, and the new line will begin without a comment marker in HDL 22-Apr-17 EE514 EE514

4/22/2017 Wizards FSM Wizard or Allows you to quickly create basic state machines Optimization Wizard or Collects information on design goals and target devices, to provide optimized results for speed, area, gate count, etc. Optimizes code for target device AND synthesis tool Design Wizard Combines FSM Wizard and Optimization Wizard into one Only available through the Wizard Toolbar (Window  Wizard Toolbar) 22-Apr-17 EE514 EE514

Wizards Logic Wizard or Wizard Toolbar Develops data flow logic 4/22/2017 Wizards Logic Wizard or Develops data flow logic Supports counters, muxes, shifters, latches, and gates Wizard Toolbar 22-Apr-17 EE514 EE514

Compilation Compilation translates state diagrams into HDL 4/22/2017 Compilation Compilation translates state diagrams into HDL Automatic error checking, logic minimization, state assignments Performs syntax check, language problems, and design problems 22-Apr-17 EE514 EE514

Compiler Configuration Options 4/22/2017 Compiler Configuration Options Access Configurations options through the menu bar: Options  Configuration Options Delete unread variables Retain output values Implied else Language 22-Apr-17 EE514 EE514

Compiler Configuration Options 4/22/2017 Compiler Configuration Options Check options Indeterminate transitions Conflicting State assignments State Assignments 22-Apr-17 EE514 EE514

Summary State diagrams can be translated into VHDL, Verilog, or ABEL 4/22/2017 Summary State diagrams can be translated into VHDL, Verilog, or ABEL Numerous toolbars are available to aid in your diagram design States and state transitions are easily added through buttons in the Draw Mode Toolbar The Output Wizard gives access to the Logic Wizard, so you can easily add output equations or conditions to any state or transition Designs are compiled and translated with a simple push button 22-Apr-17 EE514 EE514