Elevator Controller We’re hired to design a digital elevator controller for a four-floor building 00 01 10 11 1st try: Design a counter that counts up and down 00, 01, 10, 11, 10, 01, 00, ... Problem: Never stops! 2nd try: Add “Stop” button that disables counter Problem: Have to press button when elevator happens by We need a way to have user inputs into a complex system

Finite State Machines Counters - Next state based on current state If counter is in state ‘101’, next state is ‘110’ No inputs (other than reset, enable) Finite State Machines Next state is a function of the current state and the inputs If the elevator is on floor 00 and the UP button is pressed on floor 10, then move to floor 01 If current state is 00  If UP2, Next state is 01

A Finite State Machine Inputs Clock Current State Next State Next floor/ direction Current floor/ direction Combinational Logic For Next State Comb. Logic For Outputs State FlipFlops Clock Current State Next State Motor/Door Controls Example shown for elevator controller Elevator Buttons Inputs

Gumball Machine We’re building a gumball machine 15 cents for a gumball Machine has a single slot, which can take dimes or nickels Subcontractor provides a coin sensor, which has two outputs: N is true if a nickel was input D is true if a dime was input We must provide the output Open when 15 cents entered Gumball Machine FSM N D Reset Clk Open Coin Sensor Candy Release Mechanism

Gumball Machine Tabulate typical input sequences: three nickels Reset N’D’ Diagram what is going on in a state diagram S0 Note: No change provided! Tabulate typical input sequences: three nickels nickel, dime two nickels, dime two dimes dime, nickel N D N’D’ N’D’ S1 S2 D N D N N’D’ S3 [open=1] S4 [open=1] S5 [open=1] S6 Draw state diagram: Inputs: N, D, reset Output: open N’D’ S0 N S1 D S2 N’D’ S0 N S1 D S2 N’D’ S0 N S1 D S2 N D [open=1] S7 [open=1] S8 N’D’ S0 N S1 D S2 N’D’ S0 N S1 D S2 Output (open) indicated during states in which is is asserted

A More Efficient Solution 10¢ 1 5¢ 15+¢ 0¢ Q+ Next State N Input D Input Q Current State Q Current State Open Output 0¢ 5¢ 10¢ 15+¢ 1 Reset 0¢ N’D’ 0¢ N’D’ D 5¢ N N’D’ 10¢ 5¢ X N D 5¢ N 10¢ N’D’ 10¢ 15+¢ Output Table X D N+D 10¢ 15+¢ [open=1] 15+¢ 15+¢ X Reuse states whenever possible 0¢ 5¢ 10¢ Symbolic State Table X

Gumball Machine State Table Q1Q0 Current State 1 Q1+Q0+ Next State N Input D Input Q1Q0 Current State Open Output 1 Encode states into binary numbers Calculate total number of states: 4 (0¢, 5¢, 10¢, 15¢) Use as many bits as needed for the states 4 states --> 2 bits Encoding: 0¢: 00 5¢: 01 10¢: 10 15+¢: 11 1 X 1 Output Table Encoded State Table

Gumball Machine Implementation Q1Q0 DN 00 01 11 10 Q1 Q0 D N D1 Q1Q0 DN 00 01 11 10 Q1 Q0 D N D0 If we chose D FF’s, we don’t have to convert Q’s to FF inputs 1 x 1 x D1= D + NQ0Q1’ + Q0’Q1 Q1Q0 Current State Open Output 1 D2= NQ0’ + N’Q1’Q0 + NQ1 + DQ1Q0’ Open = Q1Q0 Note that the output is a function of only the state

Inputs FSMs change state based on clock edges I.e. Rising clock edge clocks all FFs This part can change only when clock “ticks” Combinational Logic For Next State Comb. Logic For Outputs State FlipFlops Clock Inputs Synchronous Inputs: Change in synch with the clock. Obey setup and hold time. This part can change at any time Asynchronous Inputs: Change at any time. May violate setup and hold times.

Asynchronous vs. Synchronous Inputs Example: Elevator pushbuttons Arrive at any time Usually asserted for many clock cycles FSM logic must not make any assumptions about input timing Example: Data arriving on a serial line from a computer Arrive synchronized exactly to a clock One bit of data per clock cycle FSM can assume that data changes once per clock cycle

Parity Checker Assert output (parity) whenever input bit stream (synchronous) has odd # of 1's 1 Clk Input Output Reset State Diagram In’ Q Present State In Input Q+ Next State Even 1 Odd Even [0] Q Present State Parity Output Even Odd 1 In In Odd [1] Parity = Q In’ Q+ = Q Å In

Parity Checker Q+ = Q Å In Parity = Q In T Q Pre Clr Parity In Reset D Q Clr Parity Reset D FF Implementation T FF Implementation Parity Checking is a type of Synchronous Serial Input FSM A single input Input is synchronized with clock (1 bit per clock cycle) Goal is to look for patterns in the input bit stream

Pattern Matcher A string recognizer has one synchronous input (X) and one output (Z). The output is asserted whenever the input sequence …010… has been observed, as long as the sequence …100… has never been seen. This is a synchronous serial input problem Sample input/output behavior: 1. Work though sample inputs to understand problem X: 1 1 1 1 1 1 Z: 1 2. Develop FSM to recognize patterns X: 1 1 1 1 3. Implement using standard techniques Z: 1 1 1

Pattern Matcher 1 1 1 1 1 1 0+1 Pick a reset state. Draw paths for strings to recognize (010 and 100) Fill in all of the missing transitions (each state needs a path out for 0 and 1) Reset signal places FSM in S0 Reset S0 [0] 1 ...0 ...1 State S3: have recognized …010 if next input is 0 then have …0100 (state S6) if next input is 1 then have …0101 = …01 (state S2) S1 [0] S4 [0] 1 1 1 State S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0 ...10 S2 [0] S5 [0] 1 ...01 State S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1 1 S3 [1] S6 [0] ...100 State S2: if input is 1, then have …1 (state S4) 0+1 Outputs 1 State S5: recognizes …10 if input is 1, then have …01 (state S2) ...010 Loops in State

Pattern Matcher - Implementation S0 [0] S1 S2 S3 [1] S4 S5 S6 0+1 Reset 1 000 Current State Input Next State Q2 Q1 Q0 X 1 100 001 101 010 110 011 Assign each state a binary number Make the state transition table Make the output table

Pattern Matcher - Implementation S0 [0] S1 S2 S3 [1] S4 S5 S6 0+1 Reset 1 000 001 010 011 110 101 100 Current State Output Q2 Q1 Q0 Z 1 X Build the FSM: Use three FF’s Build next state logic based on state transition table Build output logic based on output table Assign each state a binary number Make the state transition table Make the output table