IRC Roll-Out/Plenary 4/4 Technology Node identified by xx90 –Minimum Half-Pitch of Metal 1 of either DRAM or Logic –Logic node presently being represented by: (M1 Half-Pitch + Printed Gate Length)/2 System Drivers in National Electronic Manufacturers Initiative (NEMI) Roadmap will be reviewed in July Meeting 2003 Executive Summary Outline will Include Wireless Leave Current 3-year Columns of 2001 ITRS in 2003 ITRS Long-Term Columns for Reader Convenience –2yr Basis for Long Term Years will be discussed by IRC for 2005 ITRS

Yoshimi-san Proposal: 1. Define the technology node by the minimum half-pitch of metal-1, either in DRAM or MPU. 2. Add a header before the node number to distinguish from the non-ITRS nomenclature. As a header, use half-pitch (hp, 1/2p, HP) ex. hp90nm technology, 1/2p-65nm technology, etc.

Table Data from Yoshimi Proposal : Directly measurable, technologically unambiguous. Can smoothly trace the possible crossover of HP from DRAM to MPU. Can be independent of non-ITRS convention. Consistent with ITRS2001. Quite a minor alteration. ITRS can stay ITRS.

(3) Poly Pitch One Possible Solution: Stay Technology Node Unchanged but To Define and Describe the Logic Half Pitch (=Pitch/2) as M1 in the 2003 ITRS MPU/ASIC DRAM Metal pitch =Cell Pitch (2) Contacted Metal 1 (M1) pitch Logic

N90nm Node N65nm Node

Backup

2003 Outline Foreword – P.Gargini Introduction – TSIA/B.Doering –Overview –Technology Requirements –Potential Solutions –Wireless Technology - ESIA –Overall Roadmap Process and Structure – A. Allan Technology Characteristics/Requirements Tables Technology Nodes [Targets?] Drivers for ITWG Technology Requirements

2003 Outline Grand Challenges – Yoshimi-san/A.Allan –Overview –In the Near Term (through 2009) Enhancing Performance Cost-effective Manufacturing –In the Long Term ( ) Enhancing Performance Cost-effective Manufacturing Difficult Challenges – ITWG Chair Summary –Tables are contributed by ITWGs

2003 Outline Overall Roadmap Technology – A.Allan Characteristics –Background –Overview of 2003 Revisions Definitions Roadmap Timeline Product Generations and Chip-size Model Trends [chip size, lithographic field, wafer size, etc.] Performance of Packaged Chips Electrical Defect Density Power Supply and Dissipation Cost

2003 Outline Glossary – K or J - SIA/A.Allan –Characteristics of Major Markets –Chip and packagephysical and electrical attributes –Fabrication attributes and methods –Maximum substrate diameter –Electrical design and test metrics –Design and test

2003 Outline Technology Working Group Reports - ITWGs –System Drivers –Design –Test and Test Equipment –Process Integration, Devices and Structures Emerging Research Devices –Front-end Processes –Lithography –Interconnect –Factory Integration –Assembly and Packaging –Environment, Safety and Health –Yield Enhancement –Metrology –Modeling and Simulation –Other?

2003 Outline ITWG Reports Required Contents - ITWGs –Scope –Difficult Challenges –Technology Requirements –Potential Solutions –Cross-cut ITWG Issues –Inter Focus ITWG Discussion

2003 Citations Cited Works / Footnoted Materials – ITWGs/L.Wilson –ITWG submits copies of cited works information title page showing all authors publisher, Vol. No., date published, location published, pages used –ITWG submits permission for use

2003 Table Templates Difficult Challenges Tables –5 challenges nm / Through 2009 –5 challenges <45nm / Beyond 2009 Technology Requirements Tables –Proposed Near-term Year Header for All Tables –Proposed Long-term Year Header for All Tables