1 Machine-Level Programming I: Basics Comp 21000: Introduction to Computer Organization & Systems Spring 2015 Instructor: John Barr * Modified slides from the book “Computer Systems: a Programmer’s Perspective”, Randy Bryant & David O’Hallaron, 2011

2 Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Intro to x86-64

3 Intel x86 Processors Totally dominate laptop/desktop/server market  but not the phone/tablet market (that’s ARM) Evolutionary design  Backwards compatible up until 8086, introduced in 1978  Added more features as time goes on Complex instruction set computer (CISC)  Many different instructions with many different formats  But, only small subset encountered with Linux programs  Hard to match performance of Reduced Instruction Set Computers (RISC)  But, Intel has done just that!  In terms of speed. Less so for low power.

4 Intel x86 Evolution: Milestones NameDateTransistorsMHz K5-10  First 16-bit processor. Basis for IBM PC & DOS  1MB address space K16-33  First 32 bit processor, referred to as IA32  Added “flat addressing”  Capable of running Unix  32-bit Linux/gcc uses no instructions introduced in later models Pentium 4F M  First 64-bit processor, referred to as x86-64 Core i M  64-bit multi-core, low power

5 Intel x86 Processors: Overview X86-64 / EM64t X86-32/IA32 X Pentium Pentium MMX Pentium III Pentium 4 Pentium 4E Pentium 4F Core 2 Duo Core i7 IA: often redefined as latest Intel architecture time ArchitecturesProcessors MMX SSE SSE2 SSE3 SSE4

6 Intel x86 Processors, contd. Machine Evolution  M  Pentium M  Pentium/MMX M  PentiumPro M  Pentium III M  Pentium M  Core 2 Duo M  Core i M Added Features  Instructions to support multimedia operations  Parallel operations on 1, 2, and 4-byte data, both integer & FP  Instructions to enable more efficient conditional operations Linux/GCC Evolution  Two major steps: 1) support 32-bit ) support 64-bit x86-64

7 More Information Intel processors (Wikipedia)Wikipedia Intel microarchitecturesmicroarchitectures

8 New Species: ia64, then IPF, then Itanium,… NameDateTransistors Itanium200110M  First shot at 64-bit architecture: first called IA64  Radically new instruction set designed for high performance  Can run existing IA32 programs  On-board “x86 engine”  Joint project with Hewlett-Packard Itanium M  Big performance boost Itanium 2 Dual-Core B Itanium has not taken off in marketplace  Lack of backward compatibility, no good compiler support, Pentium 4 got too good

9 x86 Clones: Advanced Micro Devices (AMD) Historically  AMD has followed just behind Intel  A little bit slower, a lot cheaper Then  Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies  Built Opteron: tough competitor to Pentium 4  Developed x86-64, their own extension to 64 bits

10 Intel’s 64-Bit Intel Attempted Radical Shift from IA32 to IA64  Totally different architecture (Itanium)  Executes IA32 code only as legacy  Performance disappointing AMD Stepped in with Evolutionary Solution  x86-64 (now called “AMD64”) Intel Felt Obligated to Focus on IA64  Hard to admit mistake or that AMD is better 2004: Intel Announces EM64T extension to IA32  Extended Memory 64-bit Technology  Almost identical to x86-64! All but low-end x86 processors support x86-64  But, lots of code still runs in 32-bit mode

11 Our Coverage IA32  The traditional x86 x86-64/EM64T  The new standard  We’ll only talk about in passing Presentation  Book presents IA32 in Sections 3.1—3.12  Covers x86-64 in 3.13

12 Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Intro to x86-64

13 Definitions Architecture: (also instruction set architecture: ISA) The parts of a processor design that one needs to understand to write assembly code.  Examples: instruction set specification, registers. Microarchitecture: Implementation of the architecture.  Examples: cache sizes and core frequency. Example ISAs (Intel): x86, IA, IPF

14 CPU Assembly Programmer’s View Programmer-Visible State  PC: Program counter  Address of next instruction  Called “EIP” (IA32) or “RIP” (x86-64)  Register file  Heavily used program data  8 named locations, 32 bit values (x86-64)  Condition codes  Store status information about most recent arithmetic operation  Used for conditional branching PC Registers Memory Object Code Program Data OS Data Addresses Data Instructions Stack Condition Codes  Memory  Byte addressable array  Code, user data, (some) OS data  Includes stack used to support procedures

15 Kernel virtual memory Memory mapped region for shared libraries Run-time heap (created at runtime by malloc) User stack (created at runtime) Unused 0 %esp (stack pointer) Memory invisible to user code brk 0xC x x Read/write segment (.data,.bss ) Read0nly segment (.init,.text,.rodata ) Loaded from the executable file Program’s View: memory Machine instructions and constants go here Variables in main() go here Variables in functions go here NOTE: MEMORY GROWS UP; 0 IS AT BOTTOM!.data = global and static variables;.bss = global variables initialized to 0;.text = code;.rodata = constants (read only)

16 Kernel virtual memory Memory mapped region for shared libraries Run-time heap (created at runtime by malloc) User stack (created at runtime) Unused 0 %esp (stack pointer) Memory invisible to user code brk 0xc x x Read/write segment (.data,.bss ) Read-only segment (.init,.text,.rodata ) Loaded from the executable file CPU’s View: fetch, decode, execute EIPEIP Registers CPU Condition Codes 1.Fetch instruction from memory (%eip contains the address in memory) Increment %eip to next instruction address

17 Kernel virtual memory Memory mapped region for shared libraries Run-time heap (created at runtime by malloc) User stack (created at runtime) Unused 0 %esp (stack pointer) Memory invisible to user code brk 0xc x x Read/write segment (.data,.bss ) Read-only segment (.init,.text,.rodata ) Loaded from the executable file CPU’s View EIPEIP Registers CPU Condition Codes 2. Decode instruction and fetch arguments from memory (if necessary) Operand could come from R/W segment, heap or user stack

18 Kernel virtual memory Memory mapped region for shared libraries Run-time heap (created at runtime by malloc) User stack (created at runtime) Unused 0 %esp (stack pointer) Memory invisible to user code brk 0xc x x Read/write segment (.data,.bss ) Read-only segment (.init,.text,.rodata ) Loaded from the executable file CPU’s View EIPEIP Registers CPU Condition Codes 3. Execute instruction and store results Operand could go to R/W segment, heap or user stack

19 Kernel virtual memory Memory mapped region for shared libraries Run-time heap (created at runtime by malloc) User stack (created at runtime) Unused 0 %esp (stack pointer) Memory invisible to user code brk 0xc x x Read/write segment (.data,.bss ) Read-only segment (.init,.text,.rodata ) Loaded from the executable file CPU’s View EIPEIP Registers CPU Condition Codes 1. Repeat: Fetch next instruction from memory (%eip contains the addess in memory)

20 Example See: ex.html Much simpler than the IA32 architecture. Does not make the register file explicit. Uses an accumulator (not in IA32).

21 text binary Compiler ( gcc -S ) ( -S means stop after compiling) Assembler ( gcc or as ) Linker ( gcc or ld ) C program ( p1.c p2.c ) Asm program ( p1.s p2.s ) Object program ( p1.o p2.o ) Executable program ( p ) Static libraries (.a ) Turning C into Object Code  Code in files p1.c p2.c  Compile with command: gcc –m32 –O1 p1.c p2.c -o p  Use basic optimizations ( -O1 )compile to 32 bit code (-m32)  Put resulting binary in file p

22 Compiling Into Assembly C Code int sum(int x, int y) { int t = x+y; return t; } Generated IA32 Assembly sum: pushl %ebp movl %esp,%ebp movl 12(%ebp),%eax addl 8(%ebp),%eax popl %ebp ret Obtain with command gcc –O0 -S –m32 sumIt.c Produces file code.s- m32 means generate 32-bit code Some compilers use instruction “ leave ” Use the –O0 flag (dash uppercase ‘O’ number zero) to eliminate optimization. Otherwise you’ll get strange register moving.

23 Looking at Assembly Code (method 1) C Code int sum(int x, int y) { int t = x+y; return t; } Generated IA32 Assembly sum: pushl %ebp movl %esp,%ebp movl 12(%ebp),%eax addl 8(%ebp),%eax popl %ebp ret Obtain with command gcc –O0 -g –m32 sumIt.c Produces file code.s- m32 means generate 32-bit code -g puts in hooks for gdb Some compilers use instruction “ leave ” Use the –O0 flag (dash uppercase ‘O’ number zero) to eliminate optimization. Otherwise you’ll get strange register moving.

24 gdb run with executable file a.out  gdb a.out quit  quit running  run  stop Reference:

25 gdb examine source code:  list firstLineNum, secondLineNum  where firstLineNum is the first line number of the code that you want to examine secondLineNum is the ending line number of the code. break points  break lineNum  lineNum is the line number of the statement that you want to break at. debugging  step// step one C instruction (steps into)  stepi// step one assembly instruction  next// steps one C instruction (steps over)  where// info about where execution is stopped

26 gdb Viewing data  print x  This prints the value currently stored in the variable x.  print &x  This prints the memory address of the variable x.  display x  This command will print the value of variable x every time the program stops.

27 gdb Getting low level info about the program  info line lineNum This command provides some information about line number lineNum including the memory address (in hex) where it is stored in RAM.  disassem memAddress1 memAddress2 prints the assembly language instructions located in memory between memAddress1 and memAddress2.  x memAddress This command prints the contents of the memAdress in hexadecimal notation. You can use this command to examine the contents of a piece of data. There are many more commands that you can use in gdb. While running you can type help to get a list of commands.

28 Assembly Characteristics: Data Types “Integer” data of 1, 2, or 4 bytes  Data values  Addresses (untyped pointers) Floating point data of 4, 8, or 10 bytes No aggregate types such as arrays or structures  Just contiguously allocated bytes in memory

29 Assembly Characteristics: Operations Perform arithmetic function on register or memory data Transfer data between memory and register  Load data from memory into register  Store register data into memory Transfer control  Unconditional jumps to/from procedures  Conditional branches

30 Assembly Language Versions There is only one Intel IA-32 machine language (1’s and 0’s) There are two ways of writing assembly language on top of this:  Intel version  AT&T version The gcc compiler uses the AT&T version. That’s also what the book uses and what we’ll use in these slides. Most reference material is in the Intel version

31 Assembly Language Versions There are slight differences, the most glaring being the placement of source and destination in an instruction:  Intel: instruction dest, src  AT&T: instruction src, dest Intel code omits the size designation suffixes  mov instead of movl Intel code omits the % before a register  eax instead of %eax Intel code has a different way of describing locations in memory  [ebp+8] instead of 8(%ebp)

32 Code for sum 0x : 0x55 0x89 0xe5 0x8b 0x45 0x0c 0x03 0x45 0x08 0x5d 0xc3 Object Code Assembler  Translates.s into.o  Binary encoding of each instruction  Nearly-complete image of executable code  Missing linkages between code in different files Linker  Resolves references between files  Combines with static run-time libraries  E.g., code for malloc, printf  Some libraries are dynamically linked  Linking occurs when program begins execution Total of 11 bytes Each instruction 1, 2, or 3 bytes Starts at address 0x401040

33 Machine Instruction Example C Code  Add two signed integers Assembly  Add 2 4-byte integers  “Long” words in GCC parlance  Same instruction whether signed or unsigned  Operands: x :Register %eax y :MemoryM[ %ebp+8] t :Register %eax –Return function value in %eax Object Code  3-byte instruction  Stored at address 0x80483ca int t = x+y; addl 8(%ebp),%eax 0x80483ca: Similar to expression: x += y More precisely: int eax; int *ebp; eax += ebp[2]

34 Machine Instruction Example C Code  Three variables Assembly  Use registers or memory locations  Can “name” memory locations  Memory location names are called “labels”  A label can represent a “variable” or a “function name” Object Code  3-byte instruction  No labels allowed Symbol table  Assembler must change labels into memory locations  To do this, keeps a table that associates a memory location for every label  Called a symbol table int t = x+y; addl 8(%ebp),%eax 0x80483ca: Similar to expression: x += y More precisely: int eax; int *ebp; eax += ebp[2]

35 Disassembled Disassembling Object Code Disassembler objdump -d p Otool –tV p // in Mac OS  Useful tool for examining object code  -d means disassemble  p is the file name (e.g., could be a.out)  Analyzes bit pattern of series of instructions  Produces approximate rendition of assembly code  Can be run on either a.out (complete executable) or.o file c4 : 80483c4: 55 push %ebp 80483c5: 89 e5 mov %esp,%ebp 80483c7: 8b 45 0c mov 0xc(%ebp),%eax 80483ca: add 0x8(%ebp),%eax 80483cd: 5d pop %ebp 80483ce: c3 ret

36 Disassembled Dump of assembler code for function sum: 0x080483c4 : push %ebp 0x080483c5 : mov %esp,%ebp 0x080483c7 : mov 0xc(%ebp),%eax 0x080483ca : add 0x8(%ebp),%eax 0x080483cd : pop %ebp 0x080483ce : ret Alternate Disassembly Within gdb Debugger gdb p disassemble sum  Disassemble procedure x/11xb sum  Examine the 11 bytes starting at sum Object 0x401040: 0x55 0x89 0xe5 0x8b 0x45 0x0c 0x03 0x45 0x08 0x5d 0xc3

37 Assembly sum.0: pushl%ebp movl%esp, %ebp subl$4, %esp movl12(%ebp), %eax addl8(%ebp), %eax leave ret.sizesum.0,.-sum.0.globl main: pushl%ebp movl%esp, %ebp subl$8, %esp andl$-16, %esp subl$16, %esp movl$0, %eax leave (GNU) Direct creation of assembly programs In.s file % gcc –S p.c Result is an assembly program in the file p.s Assembler directives Assembly commands Symbols

38 Features of Disassemblers Disassemblers determine the assembly code based purely on the byte sequences in the object file.  Do not need source file Disassemblers use a different naming convention than the GAS assembler.  Example: omits the “l” from the suffix of many instructions. Disassembler uses nop instruction (no operation).  Does nothing; just fills space.  Necessary in some machines because of branch prediction  Necessary in some machines because of addressing restrictions

39 What Can be Disassembled? Anything that can be interpreted as executable code Disassembler examines bytes and reconstructs assembly source % objdump -d WINWORD.EXE WINWORD.EXE: file format pei-i386 No symbols in "WINWORD.EXE". Disassembly of section.text: : : 55 push %ebp : 8b ec mov %esp,%ebp : 6a ff push $0xffffffff : push $0x a: dc 4c 30 push $0x304cdc91

40 Machine Programming I: Summary History of Intel processors and architectures  Evolutionary design leads to many quirks and artifacts C, assembly, machine code  Compiler must transform statements, expressions, procedures into low-level instruction sequences Assembly Basics: Registers, operands, move  The x86 move instructions cover wide range of data movement forms Intro to x86-64  A major departure from the style of code seen in IA32