ITRS Test TWG Don Edenfeld April 20 th, 2004 Spring Workshop - Stressa, Italy

Attendees Rene Segers, Philips Robert van Rijsinge, Philips Peter Muhmenthaler, Infineon Davide Appello, ST Microelectronics Tom Williams, Synopsys Burnie West, NPTest Don Edenfeld, Intel Anzou-san, Toshiba, DFT SWG Noguchi-san, NECEL, ATE SWG

Roadmap Plans 2004 Update Minor changes to most tables Increased focus on analog/RF table, introduction of power device requirements 2005 Revision Reliability Screens Merge of logic tables Merge embedded memory with SOC Addition of EDA DFT tools and DFx content Addition of test & burn-in sockets and test interface boards

Cross-TWG Outcomes Assembly & Packaging New package technologies have potential impact on test, requires further evaluation Factory Integration Further dialog on intelligent yield management systems to support increases use of adaptive test Design Further discussion required to close on handling of DFT content of the roadmap – what & where Interconnect Increasing delay on local interconnect will have a dramatic impact on test methods – requires further evaluation Yield Enhancement Not on Spring schedule, but need dialog