Slide Interconnect Update –Mandeep Bamal –Christopher Case –Alexis Farcy –Robert Geffken –Dirk Gravesteijn –Harold Hosack –Mauro Kobrinsky –Tomoji Nakamura –Eric Ou-Yang –Michele Stucchi –Detlef Weber –Osamu Yamazaki

Slide IRC Feedback and Errata Should Printable Electronics be addressed? Table and figure numbering errors (multiple) Missing reference to reference Error in keff Long Term 2014

Slide 3 Dynamic Power Increasing concern about rising dynamic power in the interconnect stack Influence of number of functions (N), activity (A) and frequency (F) Potential new performance metric Impacts effective k roadmap –Drives reduction in parasitic capacitance P = (NAF)CV 2

Slide 4 Multi-core impact on interconnect Need to consider splitting metrics into: –In-core (intra-tile) –Inter-core (inter-tile) New bandwidth requirements Wiring lengths change –Critical path reduced (in core) –Mechanical integrity challenges will change –Jmax changes –Hierarchical structure may no longer be necessary Converge to more fine pitch local/intermediate wires Power and ground delivered through grid –Global delay challenge relaxed –3D may include multi-core