ECE 477 Design Review Team 4  Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee

Outline Project overviewProject overview Project-specific success criteriaProject-specific success criteria Block diagramBlock diagram Component selection rationaleComponent selection rationale Packaging designPackaging design Schematic and theory of operationSchematic and theory of operation PCB layoutPCB layout Software design/development statusSoftware design/development status Project completion timelineProject completion timeline Questions / discussionQuestions / discussion

Project Overview RFID DigiJocks DigiJock shoppers also like to shop at… AD Targeting ads… Reaching demographics… The future of advertising!

Project-Specific Success Criteria RFID DigiJocks Decode a valid shopper RFID tag.Decode a valid shopper RFID tag.

Project-Specific Success Criteria Retrieve shopper’s characteristics from a database indexed by decoded ID.Retrieve shopper’s characteristics from a database indexed by decoded ID. RFID DigiJocks What does this DigiJock like?

Project-Specific Success Criteria Load “general” and targeted advertisements from a database.Load “general” and targeted advertisements from a database. RFID DigiJocks Where is this ad?

Project-Specific Success Criteria Display targeted advertisement images on a local LCD in response to current shopper’s ID.Display targeted advertisement images on a local LCD in response to current shopper’s ID. RFID DigiJocks AD

Project-Specific Success Criteria Display “general” advertisement images on a local LCD when valid RFID tag is not detected.Display “general” advertisement images on a local LCD when valid RFID tag is not detected. RFID DigiJocks HI

Block Diagram Microcontroller (MC9S12NE64) Level Shifter (Max3322) LCD Controller (SLCD) RFID Reader (TRRO1OEM) RFID tags 2 CLOCK 1 Push Button SD Card Reader (BOB-00204) RJ Voltage Regulator 3.3V Microcontroller (MC9S12NE64) Level Shifter (Max3322) LCD Controller (SLCD) RFID Reader (TRRO1OEM) RFID tags 2 CLOCK 1 Push Button SD Card Reader (BOB-00204) RJ Voltage Regulator 3.3V SCI SPI Ethernet SCI SPI Ethernet

Component Selection Rationale Agatha’s Major ComponentsAgatha’s Major Components –Microcontroller MC9S12NE64 Freescale FREE + DevKit On board 2 Channels

Component Selection Rationale Agatha’s Major ComponentsAgatha’s Major Components –RFID Reader TRR01OEM Up to inches* 6 x 6 x 1.5 cm YES YES (round / 18” diameter) $78.00 *tag dependent **includes license fee

Agatha’s Major ComponentsAgatha’s Major Components –Display driver $429 Component Selection Rationale *includes external RAM SLCD SCI $240 (discounted)

Packaging Design Outer KioskOuter Kiosk –5.7” LCD Display –5’ for eye-level viewing –Wood construction –Weighted

Packaging Design Inner KioskInner Kiosk –Circuitry on floor –Power/Ethernet –LCD Screen –RS-232 runs 15’ to RFID reader

Packaging Design Microprocessor (HC9S12NE64) Serial Port 15.9 Ethernet 31 Level shifter 3.8 I/O Header Serial Port SPI Header 103 (Dimensions in mm)

Schematic/Theory of Operation Main functionsMain functions –Read RFID Tags –Choose a display image –Retrieve image data from updatable SD card –Communicate / update data with Ethernet –Send image data to LCD screen –User interaction with display

Schematic/Theory of Operation Basic Power RequirementsBasic Power Requirements –All components run at 3.3V –On board voltage regulator –Microcontroller voltage regulator

Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER

HEADER Power/Ground header for 5V Wall-wart DIODE/FUSE REGULATOR 278R V regulator Diode/Fuse for protection

Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER MICRO

MC9S12NE64 I/O SCISPI ETHERNET Decoupling Caps Interfacing 3.3 Voltage Rail Ground Rail 3.3 Voltage Rail Ground Rail DECOUPLING CAPS D CAP CLOCKING BDM

Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER ETHERNET

RJ-45 Connector RJ-45 DECOUPLING CAPS PULL UP Pull Up Resistors Freescale’s suggested layout Decoupling caps 3.3 Voltage Rail

Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER CLOCKING BDM

CLOCKING BDM Freescale’s suggested layout 3.3 Voltage Rail Ground Rail HEADER BDM with external reset switch Clocking - 25MHz RESET SWITCH 25 MHz Oscillator CAP / RES network

Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER SCI SERIAL

Both SCI ports Pinned out HEADER Level Shifter MAX3222 Level Shifter CAP / RES NETWORK Suggested Layout SERIAL PORTS SLCD and RFID connections

Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER

SPI Pinout HEADER 3.3 Voltage Rail Ground Rail SPI interfaces with SD Card Reader Status LED’s using PG port GPIO STATUS LED’S 3.3 Voltage Rail

Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER I/O & USER INPUT

3.3 Voltage Rail I/O & USER INPUT I/O Header Optical Isolator GPIO Header 3.3 V Ground Header for Push Button OPTICAL ISOLATOR PUSH BUTTON

Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER

PCB Layout Main considerationsMain considerations –Parallel power and ground rails –Decoupling Capacitors near components –Transmit and Receive lines uninterrupted –Ethernet / Clocking circuits isolated

POWER PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

PCB Layout Main power and ground rails parallel Minimal current looping Trace width of 60mil POWER

PCB Layout Main power and ground rails parallel Minimal current looping Trace width of 60mil POWER Header easily accessed on edge HEADER DIODE& FUSE Diode / Fuse protection REGULATOR On board regulator Status LED’s STATUS LEDs

PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

MICRO Clocking/BDM Ethernet Decoupling Caps CLOCKING BDM ETHERNET ETHERNET CAPS CAP CAPS

PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

ETHER- NET RJ-45 on edge RJ-45 RESIST / CAPS Clear, short path for traces Resist and Caps

PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

CLOCKING BDM SPI SPI for SD pinned out CLOCKING CAPS Clocking isolated OSC BDM pinned out BDM HEADER SWITCH

PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

SCI SERIAL SCI Traces Layer shifter on bottom LEVEL SHIFTER HEADER SCI Pinout Ports on edge PORT

PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

I/O & USER INPUT Extra I/O Pinouts PORT Optical Isolator OPTICAL ISOLATOR PUSH BUTTON HEADER External User Input

PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

Software Design/Development Status Basic interfacing of peripheralsBasic interfacing of peripherals –SCI, SPI, GPIO RFID systemRFID system –Antenna and reader communicating SD CardSD Card –Attempting card communication LCD displayLCD display –Transferring of bitmaps

Project Completion Timeline TASKDESCRIPTIONWeek 9Week 10Week 11Week 12Week 13Week 14Week 15 Hardware Revise Schematic Design Revise PCB Layout Component Soldering Board Testing Software Initial Peripheral Communication SLCD Communication SLCD Image display RFID Communication RFID tag reading SPI/SD card read and write Image Display Algorithm Ethernet Initialization FAT File System Design Update Files through Ethernet Packaging Kiosk Prototyping Kiosk Construction Hardware Integration Documentation User Manual Final Presentation/Documentation

Questions / Discussion

Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER

PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER