Proposal for the read out system for the future Si. Vertex Detector with signal processing and hit data production for a fast track trigger ? M. Pernicka

Different cap. load ns Theoretical time window for the trigger working with 40 MHz for the ADC, in reality more wide continuous beam trigger and clock no more synchronic The pulse shape could be smaller – less occupancy Pulse shape of the second step 25 ns or less

Output of the APV25 Analogous signal hit 1mA/mip ideal case 25 ns or less Critical point for the digitization. clock must be well adjusted for every input as well as possible. You cannot aspect a flat range repeater must have a good frequency behaviour 128 output signals Depends of frequency After L0 < 160 (180) clock pulses distance to the event and < 3,8µs after L0 128 clocks12 cl.

AC toppling between APV25 and ADC with base line restore

Every input has its own data processor. The programme to find hits in the data stream of the APV25 could be from the CMS group or us ? The hit data with the position will be ready at the same time for all inputs. The processing needs the same time as the read out. Unlimited for the trigger rate (limit the APV25 and data transfer to the DAQ.

APV25 +…... ADCADC ADCADC FIFO 128 One module digitice and looks for hits for trigger proc. Most simple version Data Data FIFO 128 L0 Compare Data with Ped+ Threthhold Reorder the data and combine ? stripes after reorder of channels(?) Serial data output for the trigger proc. Compare Data with Ped+ Threthhold Reorder the data and combine ? stripes after reorder of channels (?) Serial data output for the trigger proc. Hephy Vienna Manfred Pernicka 2 event data block just behind each other FIFO n*128 1 proc. 2 proc. 6*1+2*0 = start f. e. not possible in the data stream 1 hit 2 hits Trigger data, serial 40 MHz or more Final data block for one input

ADCFIFO for data Comparat or Memory ped(con) + threshold Serial Out put for trigger processor (Sum of in input data below ped. + ped. of data above of ped) / 128 – sum ped(cor)/128 = correction factor Corrected Ped(var) for one event + threshold Comparat or (Corrected serial output for trigger processor) Data from hits + neighbours and position APV 25 A possibility to process the Data of the APV25 in 2 Steps. Every input has its own processor! The final `` program `` has to be found or we will use that of CMS for their Vertex Det. signal finding. Hephy Vienna Manfred Pernicka

Module x Hit data ready for trigger event 1 4*70*25ns or less It would be possible to create a trigger with a fixed delay to the event in steps of a clock. For that we have to create special trigger rules f.e. no more than 2 trigger in a certain time window Ev Hit data ready for trigger event 2 Module y 140*25ns or less Hephy Vienna Manfred Pernicka Trigger in phase trigger in phase

Advantage: Hit efficiency high nearly 100% Hit data are ready just after read APV25 Delay between trigger and the first data in the range 2,9µ to 3,79µs for 40 MHz. Delay between trigger and the last data in the range 6.4µs to 7.29µs for 40 MHz Depends of clock- fr. For 60 Mhz 2/3 of the time low noise: depends of dig. threshold setting track trigger resolution depends of granularity Quality and efficiency depends of the lay out of the Si det. Possible holes which we cannot cover-reduces the efficiency Problems: For a synchr. Trigger: The trigger for the APV25 needs a limitation in the case that we want a time stable trigger with a fixed delay to the trigger Has to be calculated. The time fluctuation for read out can be corrected afterwards to a fixed value. We know the time jitter. Track trigger created from Si vertex data Hephy Vienna Manfred Pernicka

Proposal for the ADC System for the Si. Vertex Det. BELLE. A, The APV25 should be driven with a clock frequency as high as possible The limits are a possible reduction of S/N and there is no guaranty that ``all`` APV25 have the same limit in speed! Fluctuation in production. Advantages: More trigger/ sec are possible because faster read out and the time distance between 2 trigger becomes smaller. (Less jitter of the trigger to the shaped analogue signal.) The hit information for the trigger arrives faster. A frequency up to 80 MHz could be possible. Disadvantages: The signals from the APV25 are short. From 25ns to 12.5ns. The time range to be used for digitations in the ADC is extreme small. Therefore the clock for the ADC must be adjusted for every channel. The data transmission between REBRO and ADC module must be fast (C-coupling) The ADC-SP can adjust for every input the phase of the clock. Steps are around 1,6ns or less. B, There should be no limit for the trigger rate and time for data processing and storing The ADC-TF2 has for every input a 2 step hit finding processor. The program could be more or less the same like it is used for CMS. Complete pipe line. The processed data from every input are ready at the same time. For the trigger data the first processor is used. The trigger data are ready just after the read out from the APV25 at the same time for all inputs. As output the VME P2 connector is used. (The step 2 processor would need the same time like step 1 Pr).. Hephy Vienna Manfred Pernicka

Event data block from all inputs 64 bit data - 2 hits (36 at the moment) S-link or ??? From every input a serial trigger data output ? 9UVME9UVME Trigger proc. COPPER ??? Trigger lines from some ADC modules buf fer

Multiplexing of Strip Channels of APV25 4141 8181 0 7 … 818 … 818 … … 818 Stage 1 CLK/16 … Stage 2 CLK/4 Stage 3 CLK 4141 … … ,1,2,... 8,9,10,... 16,17,18,... 24,25,2 6,... 0,8,16,24 | 1,9,17,25 | 2,10,... 32,40,48,56 | 33,41,49,57 | 34,42,... 64,72,80,88 | 65,... 96,104,112,120 | 97,... 0,32,64,96 | 8,40,72,104 | 16,48,80,112 | 24,56,88,120 || 1,33,65,97 | 9,... For the trigger processor the data should be ordered. 4,8 or Si. Stripes will be combined. Hephy Vienna Manfred Pernicka

Some words about the Pixel read out system of approximate 40 Mil. pixel for CMS. What exist. What we can use. What has to be changed.

4 ADC 4 times 10 bit data 4 clocks with different phase 8 clocks with different phase + condole signal Altera Daughter 9 inputs with 2 steps of FIFO P1P1 P2P2 64 (or 32 bit) bit data bus 40 MHz+4 control 9 lines with information for trigger Fast data transfer to PCI P3P3 VME protocol Altera Altera daughter with final FIFO Data for trigger Schematic of the ADC-Pixel with the possibility of single channel processing and output with data for trigger processor. (more or less exists) Hephy Vienna Manfred Pernicka 2 clocks phase shifted TTC TTC input optical connection 12 in p ut o pt

19 m m 9 Daughter cards with 4 ADC 10 bit may be it has to be modified 4 Daughter cards with Altera for signal processing and memory Daughter card with final multi event memory 9 daughter cards with 4 ADC or we use also the mother card for ADC’s Proposed: ADC module with 36 (and hope 40) Inputs mainly build by daughter cards ( now 9 ADC card, 10 may be space problem ) ADC module with 36 inputs ( only daughter cards on 1 side is now in construction for CMS pixel read out system. The reason for only 36 is, that the data flow to the DQS over a S- link is already around 400 MHz Byte. The prototype without firmware is ready since (serial outputs for trigger information are foreseen. ) Hephy Vienna Manfred Pernicka Would be critical

S - L In k B uf 15*128*32 20 events 12inputopto12inputopto 12inputopto12inputopto 12inputo12inputo in 15*128*32 FIFO1 2in 6*128*32 3in 6*128*32 9in 6*128*32 TTrx V M E (2 buses to load Altera) ADC+Amp+TImINg+TeStfaSIADC+Amp+TImINg+TeStfaSI 9 DAC test 55 6 TW Delay 32+5 FIFO2 8K*72 FIFo ERROR FIFO2 8K*72 FIFO ERROR locbus1 locbus2 Loadbus1 loadbus2 M u l ti pl FIFO 8K*72 2K*72 spy. I2C Link from opt. Receiver to TTCrx TW cable optoparametabus Addre ss- comp Opt.receiver Altera 70x 1 2 Clo 80 MHz clockenabel 88 Clock buffer switch and symmetr I2C 30 En for link 90 da 9 cl Buf.+ gate TTS-Buf TTS Ext Clo.+ Test B uf Buffer for36 out puts trig LVDS limit in pins may be single output 9 when possible or 6 Strobe -Buf Principe of the ADC for pixel read out with opt. inputs (now in construction nearly finished) Hephy Vienna Manfred Pernicka

Layout for the daughter card of the Altera EP1S20_F672 with EPROM and Voltage regulator (exist) 14 mm side elevation Voltage regulator EPROM Altera ADC version for pixel read out We can use 360 input/output That limits the number of ADC (one ADC min. 8+1) Every output is serial terminated Hephy Vienna Manfred Pernicka

4 connestors, each with 100 pins

4 ADC and test system on one card

Module to test ADC- and Altera daughter card Daughter card with 4 inputs ADC Daughter card with Altera Delay IC’s PHOS-4 Long transmission line serially terminated study of pulse deformation Hephy Vienna Manfred Pernicka

Final ADC module for the pixel system Optical receiver Opt. input for TTC Optical link TTCrx S-link or 36 outputs with seriell hit data