High Speed Digital Systems Lab Spring 2008 Students: Jenia Kuksin Alexander Milys Instructor: Yossi Hipsh Midterm Presentation Winter 2008/2009

 Design Review of project schematics before proceeding to PCB design.  Receiving feedbacks and general notes. Goal of Our Meeting

Designing High Speed Transmission Line Board which will provide an ideal vehicle for learning about Signal Integrity issues like: Reflections in Transmission Lines Cross Talk in Transmission Lines Jitter Skew Project Description

Instructor Student Controller Switching System Transmission Lines Array Experiment Environment

Block Diagram Pulser S0 0  narrow pulse 1  wide pulse Signal Splitter S1 Will be OE for splitters Transmission Lines 36 lines Termination Z(Load) Z(Source) Analog Switches Analog Switches S2 Connects One channel from 36 To scope S3 Connects One channel from 36 To scope 36 1 S5 Control for MCP195 (jitter) Controller

Description of Main Blocks will create short (0.5-1 nsec) and a long ( nsec) pulse signal with very low rise/fall time (200ps). (will be implemented by Yossi’s Group) Pulser - will create short (0.5-1 nsec) and a long ( nsec) pulse signal with very low rise/fall time (200ps). (will be implemented by Yossi’s Group) Signal Splitter – launching a signal into a transmission line and converts differential signal to single ended while only one line can be alive at the same time Analog Switches – transmit the measured voltage signal on input/output of selected transmission line to oscilloscope.

Description of Blocks Transmission Lines – will contain 36 microstrip, single ended transmission lines with different terminations. Controls all of the operation of the Board. (will be implemented by Mony’s Group) Controller – Controls all of the operation of the Board. (will be implemented by Mony’s Group)

Pulser-Block Diagram Splitter MPC94551 Oscillator 50MHz C V / 5V ECL 2-Input Differential AND/NAND Controller 3.3V ECL Programmable Delay Chip 3.3V ECL Programmable Delay Chip One Shot MC74LCX74DG CMOS 5V/3.3V CMOS 3.3V MC100EP195 MC100EP Translator MC100EPT20 Translator MC100EPT20

One Shot Simulation in Hyperlynx Pulse width from one-shot is determined by capacitor and resistor T width =9.37ns R=100 ohm C=130 pF

Signal Splitter Block Diagram 1:10 Differential Clock Driver MC100LVEP111FAG :10 Differential Clock Driver MC100LVEP111FAG 1:10 Differential Clock Driver MC100LVEP111FAG 10 Differential Termination 1:10 Differential Clock Driver MC100LVEP111FAG Differential lines 36 Amplifiers 36 Single ended lines 36 Single ended Termination Single ended lines Controller Voltage Regulator To Transmission lines From Pulser

Analog Switches Block Diagram SP6T Switch Ch1 SP6T Switch A B C D E F 36 hot lines 6 hot lines 3 Control lines 36 Transmission Lines 3 Control lines SP6T Switch Ch2 SP6T Switch A B C D E F 36 hot lines 6 hot lines 3 Control lines 3 Control lines 1 hot line 1 hot line

Single Switch Diagram SP6T Switch 6 Inputs 3 Controls Output SP6T Switch MASWCC0006 V3 We use Block of SP6T Analog Switches to connect Inputs and Outputs of transmission lines to Channels of Digital Oscilloscope.

Electrical scheme

PCB placement (preliminary) Pulser Main Power Regulation Digital Splitter Amplifiers + Local LDO Local LDO Control Transmissio n Lines Analog MUX Analog MUX Control Digital part Analog part

PCB Stackup (preliminary) Signals(microstrip) GND Vt_1v3 – stripline (mux-measurement) Vcc_3v3 Signal_control_1 Signal_control_2 Vcc_5v (Vcc_5v5)

Parts List Missing parts  SW A- GaAs SP6T Switch, Absorptive, Single Supply  CD74HCT237 – High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches -  GVA Volt-Surface Mount Monolithic Amplifer  RFC1 ADCH_80A -

Time Shedule We are at that stage

Current tasks PCB Designing – 3 weeks PCB Production – 3 weeks PCB Assembly – 3 weeks Functional tests – 1 week

Questions?