CPU BASICS, THE BUS, CLOCKS, I/O SUBSYSTEM Philip Chan

CPU Basics  We know data must be binary-coded.  We know memory is used to store data and instructions.  CPU  Fetches instructions  Decodes instructions  Performs sequence of operations on data

CPU Continued  All CPUs have 2 pieces:  Datapath Network of storage units (registers) and arithmetic logic units Connected by buses Timing of data is controlled by clocks  Control unit Responsible for sequencing data at the right place at the right time  Imagine a Water Slide, and how it is managed.  Order of people, clearance to go, landing

The Registers  A Register is a place used to store a wide variety of data  Addresses  Program Counters  Data for Program Execution  Located on Processor to be accessed quickly  Since data processing is usually done on fixed-size binary words, most computers have certain sized registers.  For this reason, 16, 32, and 64bit processors exist.

Registers Continued  Info is written, read, and transferred from register to register.  Not addressed the same way memory is addressed.  Manipulated by control unit itself.  Special registers for special tasks  Store Info  Shift Values  Compare Values  Counts  No “scratchpad registers”, that control:  Looping  Stack pointers to info  Temp Values

The ALU  Arithmetic Logic Unit  Carries out all logic and arithmetic operations  Typically 2 data inputs, 1 data output  All operations in ALU affect status register bits.  Told by Control Unit

Control Unit  Policeman/Traffic Manager of CPU  Monitors execution of:  Transfer of all information  Program Instructions  Process:  Extracts from memory  Decodes instructions  Makes sure data is in right place at right time  Tells which registers to use, and any interrupts  Manipulates correct circuitry for operation  Uses a program counter to keep track and find execution, overflows, etc.

The BUS  Set of wires that acts as datapath to connect multiple subsystems in system.  Only 1 device may use a bus at a time  This sharing bottlenecks instruction speed  Divided into 2 Categories;  Master – Initiates commands  Slave – Responds to requests of Master  Can be:  Point to Point 2 Specific component conversation  Common pathway Aka Multipoint, shared across many devices

BUS Continued  Because of this method of sharing, Bus Protocols are important.  Different lines of data include:  Data Lines – Actual Information To Be Moved  Control Lines – Permissions for bus to be used Interrupts, clock sync, requests  Address Lines – Location data should go  Power Lines – Provided electricity  Each happens within bus cycle, 2 ticks of bus clock

And Yet More BUS  Buses also divided into different types  Processor-Memory Short, high speed, closely matched to memory to maximize bandwidth  I/O Longer and allow many types of devices with varying bandwidth  Backplane Built into chassis, connects processor, I/O Devices, Memory

And Yet More BUS  PCs have own terminology in terms of BUSes  Internal  Connects CPU, Memory, Others  Expansion  Connects External Devices, Peripherals, Expansions Slots, I/O Ports  Slow, but allow for generic connectivity  Local  High-Speed for limited number of similar devices

And Yet More BUS Info  Physically little more than bunches of wires, have standards for connectors,timing, and signaling.  Synchronous  Only at Tick, Clocked, synchronized at clock’s rate  Length of the bus imposes restrictions on rate and time.  Asynchronous  Control lines control operations  Complex protocol required to enforce instruction timing  Scale better with technology and support more devices

BUS Arbitration  Required when there is more than 1 master device  Determines which Bus is used at a point in time for what reason  Daisy Chain Arbitration  Uses Grant Bus control line that is passed down from bus of highest priority to lowest.  Centralized parallel arbitration  Each devices has request control line to bus, and centralized arbiter selects who gets the bus  Distributed Arbitration using Self-Selection  Similar to Centralized but instead of central authority, devices themselves choose who has highest priority  Distributed arbitration using Collision Detection  Each devices allowed to make request, any collisions mean another request is needed

Clocks  Every computer contains Clock to regulate instructions to be executed.  Without clocks speed of digital gates would be unpredictable, and regulation of programs would be impossible  Measured in Clock Cycles  This is simply frequency’s reciprocal  Besides Individual Clock Cycles, There are Bus Clocks for other uses  Overclocking  Pushing bounds of components to make more efficient process execution times

INPUT/OUTPUT SUBSYSTEM  I/O Allows us to communicate with the computer  Transfer of data with peripherals and memory  An Interface handles all the transfers of data  2 Types  Memory-Mapped I/O Registers in interface, no difference between computer’s memory allocations and current I/O Devices  Instruction-Based I/O Specialized instructions for I/O No memory required, but requires specific instructions  Interrupts are essential in I/O as they notify the CPU more efficiently than atypical data calls