Lecture 5. Sequential Logic 3 Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research

Korea Univ What Determines Clock Speed? What is the operating clock frequency of your computer?  Why does the atom processor on your netbook run at 1.4GHz?  Why does the Core 2 Duo on your notebook run at 2.0GHz?  Why can’t run at 100GHz or 1000GHz?  We are going to answer to this question today 2

Korea Univ Synchronous Sequential Circuit As studied, virtually all the synchronous sequential circuits (including CPU) are composed of  Flip-flops cascaded  Combinational logic between flip-flops Pipeline is also implemented in this way We are going to talk deep about this in computer architecture class next semester 3 R1 R2 R3 Q2D2D3 D1 CL1 CL2 Q3

Korea Univ Short Answer Suppose that the circuit does addition (+1) to the input (D1)  CL1 does “+1”  So, we want to get “D1+1” after 1 clock cycle 4 R1 R2 Q2 D2 D1 CL1 CL1 delay If delay is longer than 1ns, the circuit can’t run at 1GHzIf delay is shorter than 1ns, the circuit can run at 1GHz

Korea Univ A Little Long Answer Let’s talk a little deep about what contributes to the delay Consequently what determines the clock frequency of synchronous sequential circuit 5

Korea Univ Timing Flip-flop samples D at the (rising) edge of the clock Input data in D must be stable when it is sampled  Similar to a photograph, input data must be stable around the clock edge  If input data is changing when it is sampled, metastability can occur 6

Korea Univ Input Timing Constraints Setup time  t setup = time before the clock edge that data must be stable Hold time  t hold = time after the clock edge that data must be stable Aperture time  t a = time around clock edge that data must be stable (t setup + t hold ) 7

Korea Univ Output Timing of Flip-Flop Propagation delay  t pcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) Contamination delay  t ccq = time after clock edge that Q might be unstable (i.e., start changing) Output timing is determined depending on how you implement flip- flop 8

Korea Univ Dynamic Discipline The input to a synchronous sequential circuit must be stable during the aperture (setup and hold) time around the clock edge. Specifically, the input must be stable  at least t setup before the clock edge  at least until t hold after the clock edge 9

Korea Univ Dynamic Discipline The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements 10

Korea Univ Setup Time Constraint The setup time constraint depends on the maximum delay from register R1 through the combinational logic The input to register R2 must be stable at least t setup before the clock edge 11 T c ≥ t pcq + t pd + t setup t pd ≤ T c – (t pcq + t setup )

Korea Univ Hold Time Constraint The hold time constraint depends on the minimum delay from register R1 through the combinational logic The input to register R2 must be stable for at least t hold after the clock edge 12 t ccq + t cd > t hold t cd > t hold - t ccq

Korea Univ Timing Analysis Example 13 Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps t pd = 35 ps t cd = 25 ps

Korea Univ Timing Analysis Example 14 Setup time constraint: t pd = 3 x 35 ps = 105 ps T c ≥ ( ) ps = 215 ps f c = 1/T c = 4.65 GHz Hold time constraint: t ccq + t cd > t hold ? ( ) ps > 70 ps ? No! Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps t pd = 35 ps t cd = 25 ps T c ≥ t pcq + t pd + t setup t ccq + t cd > t hold

Korea Univ Fixing Hold Time Violation 15 Add buffers to the short paths: Setup time constraint: t pd = 3 x 35 ps = 105 ps T c ≥ ( ) ps = 215 ps f c = 1/T c = 4.65 GHz T c ≥ t pcq + t pd + t setup Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps t pd = 35 ps t cd = 25 ps t ccq + t cd > t hold Hold time constraint: t ccq + t cd > t hold ? ( ) ps > 70 ps ? Yes!