Front End Processes ITRS 2012 Summer Public Conference 12 July 2012 2012 Summer Meeting FEP ITWG Contributors J. Barnett M. Walden C. Hobbs M. Goldstein M. Alessandri R. Jammy M. Watanabe P. Majhi Y. Le Tiec C. Gottschalk Tom Lii W. Y. Loh Darryl Peters

2012 ITRS FEP Sub-TWG Leadership HP MPU ASIC (Table FEP 2) Wei-Yip Loh (US) LOP (FEP 3) LSTP (FEP 4) DRAM (FEP 5) Ho Jin Cho (KR) Floating Gate Flash (FEP 6) Mauro Alessandri (EU) Charge Trapping Flash (FEP 7) PCM (FEP 8) FeRAM (FEP 9) Yukinobu Hikosaka (JP) Starting Materials (FEP 10) Mike Walden (US) Mike Goldstein (US) Surface Preparation (FEP 11) Joel Barnett (US) Therm/Thin Films/Doping (FEP 12) Wei-Yip Loh (US) Etch (FEP 13) Tom Lii (US) CMP (FEP 14) Darryl Peters (US)

New Structures and Materials for Transistors and Memory Next Generation Metal Gate/High k stacks New High Mobility Channel Materials + III/V and Ge High µ Alternative Channel Mat’ls FDSOI Advanced Memory 3D Devices - Formation, Doping, Stress Smaller and new materials and 3d Need to know stress in whole area although one usually measures local load. New Memory Materials Phase Change Memory

Next Generation High k stacks New Materials impact CD Metrology Next Generation High k stacks Resolving New Materials and Processes What is the correlation between electrical properties & materials structure? How can interfaces be engineered? Theoretically determined k values X. Zhao and D. Vanderbilt, Phys. Rev. B., 233106 (2002) monoclinic cubic tetragonal k (HfO2)* 16 29 70 k (ZrO2)† 20 37 47 high-k higher-k SE Optical properties Crystal phases change optical (and electrical) properties of next- generation materials. GIXRD SE Hill et. Al. J. Appl. Phys. 103, 093712 2008 wavelength XAS

FEP Difficult Challenges Near Term Strain Engineering - continued effective use for increasing device performance - application to FDSOI and Multi-gate technologies Achieving DRAM cell capacitance with dimensional scaling - finding robust dielectric with dielectric constant of ~60 - finding electrode material with high work function Achieving clean surfaces free of killer defects - with no pattern damage - with very low material loss (<0.1 A) High-k/Metal Gate - introduction to full scale manufacturing for HP, LOP, and LSTP Application to advanced structures and materials - scaling equivalent oxide thickness (EOT) below 0.8nm while maintaining electrical performance 450mm wafers - production level quantity

FEP Difficult Challenges Long Term Continued scaling of HP multigate device in all aspects: EOT, junctions, mobility enhancement, new channel materials, parasitic series resistance, contact silicidation. Lowering required DRAM capacitance by 4F2 cell scheme or like, while continuing to address materials challenges Continued achievement of clean surfaces while eliminating material loss and surface damage and sub-critical dimension particle defects Continued EOT scaling below 0.7 nm with appropriate metal gates Continued charge retention with dimensional scaling and introduction of new non-charged based NVM technologies

2012 Logic Update Provide to Metrology new requirements USJ, 3D and new channel materials Establish criteria for deciding how new technology's will be incorporated as tables Continue to interact with PIDS Vdd and FDSOI pull-in n-III-V and p-Ge table entries

2012 Starting Materials Update Continue to monitor industry activities related to 450mm development and assess impact on the Starting Materials table entries Treated edge roll-off in chapter text for 2011; continue to assess adding metrics (model development dependent) in future updates Address wafer flatness colorization issues Continue to review progress relative to FinFET (SOI-based) adoption and revisit SOI starting layer thickness table entries, as appropriate

2012/2013 Surface Prep Update Critical particle size driver. ½ DRAM ½ Pitch is current driver but flash is smaller Modifying specification for AFM measurement of roughness to reflect decreased critical area size Address the difficult aspects of measuring low-k value due to damage/failure Address ESH aspects of III-V cleans (generation of phosphine, arsine gases) Include anti-stiction drying for pattern collapse in Potential Solutions table (typically a MEMS issue)

2012 Etch Update Gate CD variation updates With grid design rule widely used at gate layer, through pitch Lgate variation item is removed from total gate CD variation calculation Replacement gate high-K last dummy gate stack removal induced Lgate variation was added into total gate CD variation calculation Advanced gate etch chamber clean helped to improve wafer to wafer and lot to lot Lgate variations Gate LWR performance is marginal from 2012 LWR becomes largest portion of gate CD variation. High power plasma UV resist treatment is a potential LWR improvement method

2012 CMP Update Address Replacement Metal Gate (RMG) Obtained metrics from end users for RMG (Poly-open Process and metal polish) Revise RMG table. Add text for RMG post-CMP cleans Revise challenges. clarion2\Spin-off roadshow exhibits\Spinoff_roadshow_05.ppt 11 3/27/2017 10:37 PM3/27/2017 10:37 PM

FEP 2012 Summer 1-page Update For Logic: Provide to Metrology new requirements for USJ, 3D and new channel materials Continue to interact with PIDS on Vdd and FDSOI pull-in, discuss table entries for n-III-V and p-Ge Work with PIDS to Monitor and Update MPU and Leading Edge Logic technology trends, and establish criteria for deciding how new technology's will be incorporated as tables For Etch: Lgate variation addressed – LWR becomes largest portion of gate CD variation For Starting Materials: Continuing to monitor industry activities related to 450mm development and assess impact on the Starting Materials table entries Address SOI-based FinFET adoption and revisit SOI starting layer thickness table entries For Surface Prep: Revisit critical metals , ½ DRAM ½ Pitch critical particle size, AFM measurement of roughness, pattern collapse potential solutions Highlight ESH aspects of III-V cleans (generation of phosphine, arsine gases)

The FEP Story High-κ metal gate in high-volume manufacturing What’s next? FinFET introduced sooner than expected FDSOI making significant progress – expect introduction in 2013 III-V high-mobility channels in research – 2018 introduction New structures/materials = New Challenges