TEMPLATE DESIGN © Introduction New Graphene-based Logic Gates with Lower Power Consumption Kaisar Kussinov and Ainur Rakhymbay Objectives 3. Results 8. Conclusion Reference list 2. Methodology Graphene is most promising materials, which has unique electrical, optical and thermal properties. As graphene has high electrical and thermal conductivities, electrons in its structure move with very small resistance wherein with lower power release. Therefore, graphene is more attractive substitute for silicon [1]. Despite of all these advantages, there is absence of the energy gap between conduction and valence bands. Several solutions were offered to this problem, but most adopted is the patterning graphene sheets into narrow stripes called graphene nanoribbons (GNRs) [2]. As a result GNRs creates small energy gaps which is capable for implementation of FETs. To propose new design of logic gates to overcome physical limitations of silicon based logic gates and reduction of total energy for logic gates with feature size of less than 100nm. 2. Advantages Figure1. 3D model of GNRFET Fast (100 times faster than MOSFET) Light Sturdy High mobility (200,000cm 2 /Vs) Less heat dissipation High current-carrying capacity High thermal conductivity Excellent switching properties The length and width of proposed design are L=16 nm and W= 46 nm respectively. The channel width WCH is defined through the number of dimers N in the GNR lattice as (1), where dcc is the carbon to carbon distance and equals to nm. Then the gate width of GNR is computed as (2), where 2W SP is the spacing between ribbons. W CH =1.73* d cc (N+1)/2 (1) W G = (2Wsp+W CH )*n Rib (2) The channel surface potential VCS of GFET was obtained by using equation (3), where Qt is the total sum of capacitance at all the four terminals and C e is the total charge. V SC =V L +V P = (-Qt)/C e Qt=CsVs + CgVg + CdVd + Csub Vsub (3) Ce = Cs + Cg + Cd + Csub The parasitic capacitances were considered during the device simulation. They were calculated by using equation (4). C (gs-val) = 1.26* W G ( *Tox+0.015*T 2 ox) (4) C GDO =C GSO =nRib*C (gs-val) Figure2. Four ribbon GNRFET Table1. Parameter values for graphene Figure 3 and Figure 4 illustrate the IV characteristics of n type MOSFET and GNRFET respectively. These simulations were conducted in TannerEDA tools. Comparing these figures it can be concluded that linear conductance of the GNRFET is lower than of the MOSFET. Additionally, GNRFET reaches higher saturation values than MOSFET. Figure3. IV characteristic for n-type MOSFET Propagation delay, t p (ps) Average Power, P av (nJ/s) Logic Gates GNRFE T MOSFE TGNRFET MOSFE T Inverter Two-input NAND Figure4. IV characteristic of n-type GNRFET TABLE 2. Propagation delay and average power consumption of GNRFET and MOSFET ParameterValue L16 nm W46nm Tox1n 2*W SP 2.5 nm n Rib 4 N12 KP18.95e-15 F/um C GDO 2.25e-15 F C GSO 2.25e-15 F In this project GNRFET and Si-CMOS characteristics were discussed and compared interms of delay and average power. Based on the results it can be concluded that GNRFET is better than Si-CMOS for low power applications because GNRFET has lower average power and time delay than MOSFET. S. Miryala, A. Calimera, E. Macii and M. Poncino, “Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates”, IEEE Digital System Design (DSD), pp , August 2014 V. Tenace, A. Calimera, E. Macii, M. Poncino, “Pass-XNOR logic: A new logic style for P-N junction based graphene circuits,” Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, pp. 1-4, March 2014 Y-Y. Chen, A. Rogachev, A. Sangai, G. Iannaccone, G. Fiori, and D. Chen (2013). A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis Under Process Variation. IEEE/ACM Design, Automation & Test in Europe, pp P. Michetti and G. Iannaccone, “Analytical Model of One-Dimensional Carbon-Based Schottky-Barrier Transistors”, IEEE Transactions Vol.57(7), July 2010