Schedule and Issues for the Mini-1 and MMFE-8 Kenneth Johns University of Arizona.

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Presentation transcript:

Schedule and Issues for the Mini-1 and MMFE-8 Kenneth Johns University of Arizona

Mini-1 Schedule 2 TaskDuration Design 90 days (from 12/1/13) Design review and order parts 3/1/14 Layout30 days (done 3/31/14) PCB fabrication10 days PCB assembly – 20 pcs20 days (done 4/30/14) testing Mini-1 is intended for bench tests of the VMM2

MMFE-8 Schedule 3 TaskDuration Design105 days (from 12/1/14) Design review and order parts 3/1/14 Layout45 days (done 4/30/14) PCB initial fabrication + PCB initial assembly30 days PCB initial testing15 days (done 6/14/14) PCB fabrication + PCB assembly35 days (done 7/19/14) PCB testing PCB for distribution8/15/14?

ProductionSmall Quantity Parts$568000$ Fabrication$165000$ Assembly$343000$ NRE$1300$3276 Total$ $ MMFE board$229$506 1 board incl FPGA$821 MMFE Demonstrator Costs 4 Costs are in USD and include indirect costs of 26% Costs do NOT include VMM IC costs or SCA IC costs

S6-FMC board – Design complete but needs layout and production 68p Mini-SAS (from Mini-1) to 80p Molex (for BNL) adapter board – Design not started, but have an earlier 80p Molex adapter design (to 60p TE connector) to work from Test fixture (pulser board) for MMFE-8 (not thought about, not started, not scheduled) Other Boards Needed 5

Mini-1 – Can proceed in early January as Dan is available – Needs VMM2 packaging and pinout MMFE-8 – In early stages of design – Needs VMM2 packaging and pinout – Multidrop capability not settled – Power scheme(s) must be discussed and specified – Power for and configuration of FPGA must be specified (from Lorne) Outstanding Issues 6

MMFE-8 – Clock distribution must be specified – GbE connector must be specified – Input protection choice must be made – SRS I/O must be specified – Cooling is not addressed – RF cage requirement is not settled – Integration with MM chamber not specified or even thought about Outstanding Issues 7

Software and firmware – A local DAQ scheme must be baselined (IPBUS, MicroBlaze, something else, …) – Host PC configuration and control software (Python, Qt, …) – Large list of firmware tasks Multi-chip configuration UDP GbE output needs to be implemented Algorithm and output for L1DDC Run modes – bench, test beam, ATLAS … Outstanding Issues 8

I have confidence we can produce the Mini-1 on a timescale compatible with VMM2 The MMFE-8 demonstrator card will likely not be available until August, 2014 A significant software and firmware effort must also accompany this card Conclusions 9