Sub-Nyquist Reconstruction Final Presentation Winter 2010/2011 By: Yousef Badran Supervisors: Asaf Elron Ina Rivkin Technion Israel Institute of Technology

Project Overview Part of the Modulated Wideband Converter project cluster. – A system for sub-Nyquist sampling of multiband signals. Sub-module of the reconstruction block. Implemented on a single NI FlexRio Virtex-5 SX95T FPGA device. – NI LabVIEW interface

Sub-Nyquist Xampling Project Block Diagram

Project Goals Reconstruction Algorithm outline: 1.Covert complex-valued sequences to real- valued sequences. 2.Estimate power spectral density. 3.Find band edges. COMPLEX FFT!!

Input and Output Input: Sequences z[n] representing spectrum slices. At most N sequences, one per slice. Spectral support slices s Problem: Spectral support and carrier frequencies of bands are unknown. A single slice may contain more than one band (at most N/2). A single band might be divided between two slices.

Input and Output Output: A sequence of vectors, one per spectral slice. Each vector describes energy distribution in the slice; areas in the slice that hold energy. Requires high resolution vectors.

Welch’s Method for Power Estimation Algorithm —Divide the time signal into successive, overlapping blocks. —Form the periodogram for each block: —The Welsh estimate of the power spectral density is given by: (K= # of blocks) Contradiction: Maximize M for spectral resolution vs. Maximize K for better averaging results and greater spectral stability. Typical choice:

Spectrum Quantization Final step: Define band location 1.Find PSD threshold. 2.Unite support regions that are closer than. 3.Prune isolated regions with widths smaller than.

Implementation Demands Demands – 18-bit signed fixed-point representation (input). 17 bit word length 1 bit fraction length – Input rate of 20 MHz – Complex FFT – Implementation on a single FPGA Use 30% of FPGA resources.

Project Block Diagram Low rate sequences CTF module FIFO 20 MHZ Power Estimation Band detection output

Testing Environment Host.vi

Host.vi (Write) Parse data (64bit double to U32) Display Input Signal Host to FPGA FIFO (WRITE) 2048 elements 1024 Samples data Generate Sequence MUX Select 1 MHz rate Complex data Real data Img data Join numbers (U64bit)

Host.vi (Read) Write to file Display Output Signal FPGA to Host FIFO (READ) 2048 elements 1024 Samples (U64 bit) 1024 Samples (double) DBL WELCH Display and compare results

FPGA Real Split numbers (I32) Host to FPGA FIFO (READ) 2048 element s FPGA FIFO 1024 element s FPGA to Host FIFO (WRITE) 2048 elements FPGA FIFO 1024 elements FXP Img. Welch Power Spectral Estimation Spectrum Quantization

Welch PSD – Block Diagram Data out en Counter Memory Read Addr. Data out Data in Write Addr. Hamming Window Real data in Img. data in Real data Img. data Complex FFT Real data Img. data Out valid Shift reg

Quantization – Block Diagram

Welch’s Method for Power Estimation Comparison between MATLAB’s PWELCH, and my own: (M=256, R=128)

Results Complex FFT size = 1024.

Welch’s Method for Power Estimation Comparision between MATLAB’s PWELSH, and my own: (M=256, R=128)

Results Complex FFT size = 1024.

Mathematical Tools Project Workflow Algorithm Resources & requirements Understand theory and reference implementation Propose alternative and equivalent calculation MATLAB Floating-point representation 18-bit fixed point representation Simulink FXP FFT model Find an alternative fixed point FFT Solution Find implementations of required mathematical operations in VHDL NI-LabVIEW Creating a block diagram Implement algorithm on the host LabVIEW FPGA Integrate system on LabVIEW FPGA NI-FlexRIO Virtex-5 SX95T model. Debug Debug system Timing considerations Compare results

Resource Estimation New Device Utilization ( NO HOST/FPGA FIFOS) Total Slices Slice Registers Slice LUTs Block 40MHz, FFT size of 1024

Next Steps Detect bands and isolate them. Estimate carrier frequency per band. 6 low rate sequences (20MHz) instead of 1.

Next Steps (Cont.) Serial FFT! Low rate sequences (20MHz each) FIFO 1024 element s FIFO 1024 element s FIFO 1024 element s FIFO 1024 element s FIFO 1024 element s FIFO 1024 element s Complex FFT & Hamming Window PSD & Band Detection MUX High rate Calculation 120 MHz FIFO 1024 element s FIFO 1024 element s FIFO 1024 element s FIFO 1024 element s FIFO 1024 element s FIFO 1024 element s

Thank you!