Design and System Drivers Worldwide Design ITWG: T Design and System Drivers Worldwide Design ITWG: T. Hiwatashi (Japan), W. Rosenstiel (Europe), V. Kathail (USA), J.-A. Carballo (USA), A. B. Kahng (USA) Key messages: Software, system level design productivity critical to roadmap 2. Design technology is key to variability / “sigma” control 3. System-level design technology is key to power efficiency 4. Design cost will be contained through innovation 5. MtM brings new set of Design requirements/solutions 6. Initiating reliability roadmap for 2010-2011 Good morning. Here we present the work that the ITRS Design TWG has pursued in 2008, and describe the continuation of this work into our 2009 strategy. We start with our Design chapter. These are the 4 main messages we would like to communicate as 2008 ends. (Messages self-explanatory, do not delve in details here.)

Overview (2004-9) 1. Increasingly quantitative roadmap 2 Overview (2004-9) 1. Increasingly quantitative roadmap 2. Increasingly complete driver set 2009 More Than Moore extension + iNEMI synch + SW !! 2008 More Than Moore extension + iNEMI + SW !! 2007 More Than Moore analysis + iNEMI Updated Consumer Stationary, Portable architecture, and Networking Drivers 2006 Updated Consumer Stationary, Portable, and Networking Drivers 2005 Consumer Stationary, Portable, Networking Drivers Consumer Stationary, Portable Drivers ******* Do the same here as in the prior slide that looks the same – except here focus on the system drivers piece of it, and how it has evolved over the years ******* As this slides summarizes, we have been following a consistent successful strategy in the last years. There are two components to this strategy. First, we have been assembling a quantified Design Technology roadmap, one that resembles in structure the other non-Design chapters in our roadmap, a necessary improvement. Second, we have been assembling a comprehensive set of system drivers aligned by segment, thereby mirroring the increasing segmentation in the semiconductor industry. As you can see in the chart, we have been successful. Our Design Technology roadmap includes numerous metrics and carefully matching text sections in the Design Chapter. Our System Drivers chapter has been adding several new drivers over the last few years. This work, however, needs to continue and be updated yearly. Lastly, in 2007 we have started adding explicit content about More Than Moore and have started aligning our chip roadmap with the leading system roadmaps, specifically iNEMI. 2004 Consumer Portable Driver Additional Design Metrics DFM Extension System level extension System Drivers Chapter Driver study Revised Design Metrics DFM extension Revised Design Technology Metrics Revised Design metrics Design Technology metrics Explore Design metrics Design Chapter 2 2

System Level Design & SOFTWARE Hardware design productivity is growing appropriately Requirements correspond roughly with solutions Innovations pacing properly (transistors / designer / year) Large gap in software productivity possibly opening up If hardware accelerators are heavily leveraged, problem mitigated Otherwise, possibly 100X gap can affect memory size, other Adding new parameters to requirements/solutions tables Hardware design productivity - requirement Software design productivity - requirement Software design productivity (assuming only software implementation) System design productivity innovations – solutions (Fig. 1 in chapter) The first major message is about SOFTWARE. We have finally started adding specific parameter tracking for what has become a major source of design productivity enhancements, challenges, and solutions. Software brings about challenges and at the same is a required part of any semiconductor product. It affects all of our cross cutting challenges, but especially the major one for Design – design productivity / cost ! As multi-core takes off the challenge is exacerbating. As the slides shows, we see a much larger gap in SW design productivity than in HW design productivity. A key solution to close the gap in SW design productivity is the leverage of intelligent multi-core techniques, such as custom accelerator cores that do not pose a programming problem. We note in this graph that without these techniques the SW productivity challenges translates into a extremely fast growing requirement, pretty much impossible to meet. (alternative Scenario)

Impact of Design on “Sigma” (Variability) Goal Quantify “how many sigmas” can design “reduce” Approach Inventory of design techniques / tools Match inventory to parameters or correlations in model Use variability model to capture “delta” in sigmas System / SW Check overall variation Logic / function Circuit Device On the Design-for-Manufacturability side, we have started an effort to quantify the impact of novel DFM techniques on the ability to control manufacturing related parameters such the CD control parameter that we have been assessing in the last few years. We believe this is a critical effort as Design will continue to grow in importance in this control, since manufacturing tool limitations keep growing in importance, especially on the lithography side (see other chapters!). Use variability model Manufacturing Inputs (manufacturing)

Impact of Design on Power Emphasis on System Level [SW/HW] While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 5

ITRS Cost Chart 2009 (Millions of Dollars) RTL Functional Verif. Tool Set Transaction Level Modeling System Design Automation IC Implementation Tool Set Very Large Block Reuse AMP Parallel Processing Many Core Devel. Tools SMP Parallel Processing Executable Specification Transactional Memory Intelligent Testbench

More Than Moore (Design) More than Moore brings new set of requirements/solutions Will create additional inventory of parameters Existing requirements Existing solutions Existing Additional requirements Additional solutions We have directly accounted for More than Moore in our roadmap since last year. In 2008, we analyzed this topic again and started creating a set of new requirements and solutions that we believe may need to be added to account for functional diversification techniques, especially on the packaging / SiP side. This slide describes the concept and provides some initial parameter buckets. Additional E.g. System-level (packaging) Circuit (inter-chip parasitics modeling/simulation) Layout (SiP global layout) DFM (package-chip, SiP DFM)

Design and System Drivers Worldwide Design ITWG: T Design and System Drivers Worldwide Design ITWG: T. Hiwatashi (Japan), W. Rosenstiel (Europe), V. Kathail (USA), J.-A. Carballo (USA), A. B. Kahng (USA) Key messages: Design update to ORTCs: SRAM, logic, defect density models 2. Updated key system drivers: SOC-Consumer Portable, MPU 3. Frequency-power envelope remains critical for industry 4. Continuing to broaden System Drivers, but more cautiously MtM brings new System Driver parameters, 2009 “SIP fabric” Expanded cross-TWG and public activity (DAC ’09 workshop) Here we present the work that the ITRS Design TWG has pursued in 2008 for its System Drivers chapter, and describe the continuation of this work into our 2009 strategy. These are the 5 main messages we would like to communicate as 2008 ends. (Messages self-explanatory, do not delve in details here.)

Overview (2004-9) 1. Increasingly quantitative roadmap 2 Overview (2004-9) 1. Increasingly quantitative roadmap 2. Increasingly complete driver set 2009 More Than Moore extension + iNEMI synch + SW !! 2008 More Than Moore extension + iNEMI + SW !! 2007 More Than Moore analysis + iNEMI Updated Consumer Stationary, Portable architecture, and Networking Drivers 2006 Updated Consumer Stationary, Portable, and Networking Drivers 2005 Consumer Stationary, Portable, Networking Drivers Consumer Stationary, Portable Drivers ******* Do the same here as in the prior slide that looks the same – except here focus on the system drivers piece of it, and how it has evolved over the years ******* As this slides summarizes, we have been following a consistent successful strategy in the last years. There are two components to this strategy. First, we have been assembling a quantified Design Technology roadmap, one that resembles in structure the other non-Design chapters in our roadmap, a necessary improvement. Second, we have been assembling a comprehensive set of system drivers aligned by segment, thereby mirroring the increasing segmentation in the semiconductor industry. As you can see in the chart, we have been successful. Our Design Technology roadmap includes numerous metrics and carefully matching text sections in the Design Chapter. Our System Drivers chapter has been adding several new drivers over the last few years. This work, however, needs to continue and be updated yearly. Lastly, in 2007 we have started adding explicit content about More Than Moore and have started aligning our chip roadmap with the leading system roadmaps, specifically iNEMI. 2004 Consumer Portable Driver Additional Design Metrics DFM Extension System level extension System Drivers Chapter Driver study Revised Design Metrics DFM extension Revised Design Technology Metrics Revised Design metrics Design Technology metrics Explore Design metrics Design Chapter 9 9

ORTCs: New A-Factor Models (Area = A-factor  F2) Logic: A-factor = 175 NAND2 Area = 3 PPoly  8 PM2 (3 1.5 PM1)  (8  1.25 PM1) = 45 (PM1)2 = 180 F2  175 F2 SRAM: A-factor = 60 SRAM Bitcell Area = 2 PPoly  5 PM1 = 3 PM1  5 PM1= 15 (PM1)2 = 15 (2 F)2 = 60 F2 NWell Contact Active M1 Poly Contacted-poly pitch (PPoly  1.5PM1) M2 pitch (PM2  1.25PM1) Contacted-poly pitch (PPoly  1.5PM1) M1 pitch (PM1) In MPU transistor density model, A-factor is the key parameter that enables to model all other dimensions in terms of MPU M1 half pitch. In the previous ITRS, A-factor for logic and SRAM has been around 320 and 100, respectively which was determined in 2001. In 2009, we have revised A-factor based on the layout style of recent standard libraries. For logic A-factor, we define a representative NAND2 gate layout of which size is 8 M2 pitches in height and 3 poly pitches in width. From the design rule data from industry, we find M2 pitch is roughly 1.25 times M1 and poly pitch is roughly 1.5 times M1 pitch. Then, the area of NAND2 is calculated as follows and results in 180 A-factor. This A-factor is tuned against several published CPU data and finally we decide it as 175. For SRAM A-factor, similarly we define a representative SRAM bitcell layout which consists of 2 poly pitches in height and 5 M1 pitches in width. Then we can have 60 of A-factor for SRAM bitcell. 60 of A-factor is also validated with published SRAM bitcell sizes. Fitted to industry data 10

Key System Drivers Constantly Updated Consumer Driver Model 2008: Updated power model with realistic dynamic power Memory dynamic power 10X less than modeled previously Will identify key driver requirements, explore coloring E.g., excessive power beyond portable limit (1 W) Will explore RF/A/MS for future portable consumer drivers Extends existing driver (or, future “wireless” driver is possible) Also ongoing: additional parameters per Test requests Upon provision of rationale/definition: Clocks, I/Os, currents, etc. 8 W max total (2022) 4.3 W max total (2022) Our system driver chapter covers market-driven drivers – these are very active, competitive markets, that require sometimes some of the most leading edge technology. Their characteristics also depend on manufacturing technology and thus the movement in other chapters. Every year we try to update these critical drivers. This slides show what we have done with the consumer portable driver, plus a number of initiatives we are pursuing to improve these drivers’ roadmap overall. (read bullets)

SOC Consumer Portable Architecture Model (updated) - #Main Processors grows to 2, 4 and beyond - Power budget reduced to 0.5W - Die size reduces slowly to 44mm2 Function A Function B Function C Function D Function E Main Memory PE Prc. Peripherals Main Memory PE-1 Peripherals PE-2 PE-n … Prc.

Updated MPU Density/Power/Frequency M1 Half-Pitch (F) Physical Lgate (L) Decrease Pdyn and Pleak Increase Pdyn , decrease Pleak Growth of #Tr 2x / 3 year (WAS)  2x / 2 year (IS) up to 2013 Die size reduction 310mm2 (WAS)  260mm2 (IS) Unit cell size A-Factor (A) Logic: ~320 (WAS) 175 (IS) SRAM: ~100 (WAS)  60 (IS) This slide summarizes major changes in MPU density/power/frequency model. MPU M1 pitch was shifted by 2 years and faster scaling was applied up to 2013. This results in smaller M1 HP throughout the roadmap. Smaller M1 HP results in smaller capacitance and smaller leakage power for unit cells. Lgate was shifted by 1 year which implies larger gate length. Larger gate length results in larger gate capacitance so that dynamic power increases. However, since larger gate length devices have smaller leakage current, leakage power decreases. A-factor has been updated according to the previous slide, and the resulting unit cell size decreases as shown in right figure. #transistors are doubled when M1 HP reduced to 0.7x. Hence, the scaling factors for #cores per die and #transistors per core have been updated according to M1 HP reduction trends. Although the reduced cell size is compensated by increased #transistor, the previous 310mm^2 die area still needs to be reduced to have reasonable integration overhead, since the cell size reduction has great impact. To have around 30% integration overhead, die size has to decrease to 260mm^2 and this area is approximately same as the most recent Intel’s 45nm processor “Corei7” (263mm^2) and AMD’s 45nm Opteron processor “Shanhai” (263mm^2). #core/die, #tr/core 12.2% / year (WAS)  18.9% / year (~2013, IS),  12.2% / year (2014~, IS) Increased Pdyn and Pleak 13

Design Pacing, Challenges Unabated 2009: Final Lgate and M1 HP scaling impact on Drivers M1 Half Pitch 2 year delay, but faster scaling 0.7x / 3yr  0.7 / 2yr (~2013), 0.7x / 3yr (2014~) Updated MPU model (power) Physical Lgate 1 year shift This slide shows the resulting power trends from the changes in MPU density model. The right figure compares power consumption of 2008 and 2009 models. While the previous year’s power model has almost constant near 150W, 2009 model shows smaller power in near future and larger power in far future. This increasing power trend mainly comes from the faster increase in the #transistor per die calculated from the new density model. #Tr per die New A-factors Faster M1 half pitch reduction 14

Frequency-Power Envelope Remains Critical System Issue Current priorities Power #1 goal Frequency slowdown Multi-core enables tradeoff Need to track trade-off Market vigilance Yearly adjustment Possible 2009 survey 7.7% / year The Frequency-power Trade-off will Continue, and possibly Extend more than we ever imagined. Current design have power as their main constraint, then try to scale up performance, rarely based only on frequency but more often on the number of computing elements, especially multiple cores. However, each company will feature its own trade-off and market/economic forces are increasingly determining some of these choices. As a result, we need to track this specific trade-off every year and make sure we don’t miss the frequency/core/power curve trade-off. We are considering doing a 2009 blind survey on frequency from key vendors. ~2013: 18.9% / year 2014~: 12.2% / year 15

New System Drivers? At the right pace… New SIP Fabric driver proposed, draft in 2009 Others (aerospace & defense, medical, auto, FPGA) deferred 2010? 2010? 2007 2006 2006 2006 2010? Fabrics MPU SIP PE/DSP We are slowing down in the creation of new drivers, not only because of limited bandwidth, but also because it is not clear that every market will be driving a fundamental parameter in our roadmap – requires some research. As a result: New FPGA driver was suspended (until resource identified) Others (defense) eliminated to synchronize with latest iNEMI Others might be assessed in 2009 (medical, automotive) Memory AMS Markets Medical Automotive Network Office Consumer Portable Consumer Stationary A&D 16

More Than Moore Brings Alternative Set of Parameters (2009-10) Will create additional inventory of parameters CONCEPT: Current SoC scenario vs. Additional SiP scenario Consumer portable (SoC) Consumer portable (SiP) Power System Drivers Normalized Cost As we mentioned before, we have directly accounted for More than Moore in our roadmap since last year. In 2008, we analyzed this topic again and started creating a set of new requirements and solutions that we believe may need to be added to account for functional diversification techniques, especially on the packaging / SiP side. This slide describes the concept and provides some initial parameter buckets, in this case for the system drivers. As you can see, we are aiming at creating an “alternative path” for each driver, and each company will make a choice at each node for that driver, based on power, performance, cost, etc. You can see this illustrated for the consumer drivers (both). Consumer stationary (SoC) Consumer stationary (SiP) Performance System Drivers Normalized Cost

Application processor System Drivers and iNEMI (2009) Proposal to iNEMI: develop Portable System Architecture Template New Chair with domain expertise – expect deeper commitment Application processor Baseband processor Processing POWER Memory NAND Flash Memory Wireless Flash Memory / Flash COST Other (MEMS, etc.) Audio / video codec Power mgt. This is future work for iNEMI. We’d like to get a system level driver that we can link to our “SoC” drivers for better linkage between iNEMI and ourselves. I/O controller I/O transceivers Analog / I/O NOISE SENSITIVITY 18

Design & Key ITRS Cross-TWG Initiatives With Interconnect (A&P): 3D / TSV roadmapping survey With PIDS, FEP, IRC: Modeling and requirements support for CV/I  RO-based transistor metric With CSTNSG: Updated frequency, SRAM area, active area (yield) projects With More Than Moore Study Group: Definition of SIP-scenario System Driver roadmaps to complement existing SOC-scenario Driver roadmaps The first major message is about SOFTWARE. We have finally started adding specific parameter tracking for what has become a major source of design productivity enhancements, challenges, and solutions. Software brings about challenges and at the same is a required part of any semiconductor product. It affects all of our cross cutting challenges, but especially the major one for Design – design productivity / cost ! As multi-core takes off the challenge is exacerbating. As the slides shows, we see a much larger gap in SW design productivity than in HW design productivity. A key solution to close the gap in SW design productivity is the leverage of intelligent multi-core techniques, such as custom accelerator cores that do not pose a programming problem. We note in this graph that without these techniques the SW productivity challenges translates into a extremely fast growing requirement, pretty much impossible to meet. 19

While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 20

Summary Design System Drivers Software, system level design productivity critical to roadmap 2. Design technology is key to variability / “sigma” control 3. System-level design technology is key to power efficiency 4. Design cost will be contained through innovation 5. MtM brings new set of Design requirements/solutions 6. Initiating reliability roadmap for 2010-2011 System Drivers Design update to ORTCs: SRAM, logic, defect density models 2. Updated key system drivers: SOC-Consumer Portable, MPU 3. Frequency-power envelope remains critical for industry 4. Continuing to broaden System Drivers, but more cautiously MtM brings new System Driver parameters, 2009 “SIP fabric” Expanded cross-TWG and public activity (DAC ’09 workshop) Good morning. Here we present the work that the ITRS Design TWG has pursued in 2008, and describe the continuation of this work into our 2009 strategy. We start with our Design chapter. These are the 4 main messages we would like to communicate as 2008 ends. (Messages self-explanatory, do not delve in details here.) 21